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bt8960 single-chip 2b1q transceiver the bt8960 is a full-duplex 2b1q transceiver based on rockwells hdsl technol- ogy. it supports nx64 kbps transmission of more than 18,000 feet over 26 awg copper telephone wire without repeaters. small size and low power dissipation make the bt8960 ideal for line-powered voice pairgain systems capable of provid- ing four or six clear 64 kbps channels. the bt8960 is a highly integrated device that includes all of the active circuitry needed for a complete 2b1q transceiver. in the receive portion of the bt8960, a variable gain ampli?r optimizes the signal level according to the dynamic range of the analog-to-digital converter. once the signal is digitized, sophisticated adap- tive echo cancellation, equalization, and detection dsp algorithms reproduce the originally transmitted far-end signal. in the transmitter, the transmit source and scrambler operation is programma- ble via the microcomputer interface. a highly linear digital-to-analog converter with programmable gain, sets the transmission power for optimal performance. a pulse-shaping ?ter and a low distortion line driver generate the signal character- istics needed to drive a large range of subscriber lines at low-bit error rates. startup and performance monitoring operations are controlled via the micro- processor interface. c-language source code supporting these operations is sup- plied under a no-fee license agreement from rockwell. the bt8960 includes a glueless interface to both intel and motorola microprocessors. functional block diagram distinguishing features single-chip 2b1q transceiver solution all 2b1q transceiver functions inte- grated into a single monolithic device receiver gain control and a/d converter dsp functions including echo cancellation, equalization, timing recovery, and symbol detection programmable gain transmit dac, pulse-shaping ?ter and line driver supports operation from 160 to 416 kbps capable of transceiving over the ansi t1.601 and etsi etr 080 isdn test loops flexible monitoring and control glueless interface to intel 8051 and motorola 68302 processors access to embedded ?ters, perfor- mance meters and timers backwards compatible with bt8952 software api commands jtag/ieee std 1149.1-1990 compliant single +5 v power supply operation 600 mw power consumption at 288 kbps (typical) 100-pin pqfp package ?0?c to +85?c operation applications voice/data pairgain systems internet connectivity isdn basic-rate interface concentrators isdn h0 transport extended range fractional t1/e1 cellular/microcellular base stations personal communications systems (pcs) radio ports and cell switches analog receive mpu bus analog transmit variable gain ampli?r microcomputer interface line driver pulse- shaping filter program- mable gain dac analog- to-digital converter digital signal processor framer/ channel unit interface recovered data and clock transmit data
cop yright ?1997 rockwell semiconductor systems, inc. all rights reserv ed. print date: december 1997 rockwell semiconductor systems, inc. reserv es the right to mak e changes to its products or speci cations to impro v e performance, reliability , or manuf acturability . information furnished is belie v ed to be accurate and reliable. ho we v er , no responsibility is assumed for its use; nor for an y infringement of patents or other rights of third parties which may result from its use. no license is granted by its implication or otherwise under an y patent or intellectual property rights of rockwell semiconductor systems, inc. rockwell semiconductor systems, inc. products are not designed or intended for use in life support appliances, de vices, or systems where malfunction of a rockwell semiconductor systems, inc. product can reasonably be e xpected to result in personal injury or death. rockwell semiconductor systems, inc. customers using or selling rockwell semiconductor systems, inc. products for use in such applications do so at their o wn risk and agree to fully indemnify rockwell semiconductor systems, inc. for an y damages resulting from such improper use or sale. bt is a re gistered trademark of rockwell semiconductor systems, inc. slc is a re gistered trademark of a t&t t echnologies, inc. product names or services listed in this publication are for identi cation purposes only , and may be trademarks or re gistered trademarks of their respecti v e companies. all other marks mentioned herein are the property of their respecti v e holders. speci cations are subject to change without notice. printed in the united states of america order number package ambient temperature bt8960epf 100-pin plastic quad flat pack (pqfp) ?0?c to +85?c ordering information
iii n8960dsb table of contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii list of t ables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 system over view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 functional summar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 t ransmit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.2 receive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.3 t iming recover y and clock inter face . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.4 microcomputer inter face . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.5 t est and diagnostic inter face (jt ag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.1 v oice/data pairgain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.2 internet connectivity t ransport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.3 isdn basic rate inter face concentrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 t ransmit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.1 symbol sour ce selector/scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.2 v ariable gain digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1.3 pulse-shaping filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1.4 line driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 receive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.1 v ariable gain ampli er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.2 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.3 digital signal processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.3.1 digital front-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.3.2 offset adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.3.3 dc level meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.3.4 signal level meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.3.5 over ow detection and monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.3.6 far -end level meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.3.7 far -end level alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
t able of contents bt8960 single-chip 2b1q t ransceiver iv n8960dsb 2.2.4 echo canceler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.4.1 linear echo canceler (lec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.4.2 nonlinear echo canceler (nec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.5 equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.5.1 digital automatic gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.5.2 feed for ward equalizer (ffe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.5.3 error predictor (ep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.5.4 decision feedback equalizer (dfe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.5.5 microcoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.6 detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.6.1 slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.6.2 peak detector (pkd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.6.3 error signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.6.4 scrambler module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.6.5 sync detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.6.6 detector meters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 t iming recover y and clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.0.7 t iming recover y cir cuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.0.8 cr ystal ampli er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4 channel unit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.5 microcomputer interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5.1 sour ce code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5.2 microcomputer read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5.2.1 ram access registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5.2.2 multiplexed address/data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5.2.3 separated address/data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5.3 interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.5.5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.5.6 t imers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.6 t est and diagnostic interface (jt ag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2 register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2.1 0x00?lobal modes and status register (global_modes) . . . . . . . . . . . . . . . . . . 44 3.2.2 0x01?erial monitor sour ce select register (serial_monitor_sour ce) . . . . . . . . . 44 3.2.3 0x02?nterrupt mask register low (mask_low_reg) . . . . . . . . . . . . . . . . . . . . . . 45 3.2.4 0x03?nterrupt mask register high (mask_high_reg) . . . . . . . . . . . . . . . . . . . . . 46 3.2.5 0x04? imer sour ce register (timer_sour ce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.6 0x05?rq sour ce register (irq_sour ce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.7 0x06?hannel unit inter face modes register (cu_inter face_modes) . . . . . . . . . . 47 3.2.8 0x07?eceive phase select register (receive_phase_select) . . . . . . . . . . . . . . . . 48 3.2.9 0x08?inear echo canceller modes register (linear_ec_modes) . . . . . . . . . . . . . 48
t able of contents bt8960 single-chip 2b1q t ransceiver v n8960dsb 3.2.10 0x09?onlinear echo canceller modes register (nonlinear_ec_modes) . . . . . . 49 3.2.11 0x0a?ecision feedback equalizer modes register (dfe_modes) . . . . . . . . . . . 50 3.2.12 0x0b? ransmitter modes register (transmitter_modes) . . . . . . . . . . . . . . . . . . 50 3.2.13 0x0c? imer restart register (timer_restart) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2.14 0x0d? imer enable register (timer_enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2.15 0x0e? imer continuous mode register (timer_continuous) . . . . . . . . . . . . . . . 53 3.2.16 0x0f? est register (reser ved2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2.17 0x10, 0x11?tartup t imer 1 inter val register (sut1_low , sut1_high) . . . . . . . . . 53 3.2.18 0x12, 0x13?tartup t imer 2 inter val register (sut2_low , sut2_high) . . . . . . . . . 53 3.2.19 0x14, 0x15?tartup t imer 3 inter val register (sut3_low , sut3_high) . . . . . . . . . 53 3.2.20 0x16, 0x17?tartup t imer 4 inter val register (sut4_low , sut4_high) . . . . . . . . . 53 3.2.21 0x18, 0x19?eter t imer inter val register (meter_low , meter_high) . . . . . . . . . 53 3.2.22 0x20? est register (reser ved9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.23 0x1a, 0x1b?nr alarm t imer inter val register (snr_timer_low , snr_timer_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.24 0x1c, 0x1d?eneral purpose t imer 3 inter val register (t3_low , t3_high) . . . . . 54 3.2.25 0x1e, 0x1f?eneral purpose t imer 4 inter val register (t4_low , t4_high) . . . . . 54 3.2.26 0x21?dc control register (adc_control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.27 0x22?ll modes register (pll_modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.2.28 0x23? est register (reser ved10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.29 0x24, 0x25? iming recover y pll phase offset register (pll_phase_offset_low , pll_phase_offset_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.30 0x26, 0x27?eceiver dc offset register (dc_offset_low , dc_offset_high) . . . . . 57 3.2.31 0x28? ransmitter calibration register (tx_calibrate) . . . . . . . . . . . . . . . . . . . . . 57 3.2.32 0x29? ransmitter gain register (tx_gain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2.33 0x2a, 0x2b?oise-level histogram threshold register (noise_histogram_th_low , noise_histogram_th_high) . . . . . . . . . . . . . . . . . . . 59 3.2.34 0x2c, 0x2d?rror predictor pause threshold register (ep_pause_th_low , ep_pause_th_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.2.35 0x2e?crambler synchronization threshold register (scr_sync_th) . . . . . . . . . 59 3.2.36 0x30, 0x31?ar -end high alarm threshold register (far_end_high_alarm_th_low , far_end_high_alarm_th_high) . . . . . . . . . . . . . . 59 3.2.37 0x32, 0x33?ar -end low alarm threshold register (far_end_low_alarm_th_low , far_end_low_alarm_th_high) . . . . . . . . . . . . . . . 59 3.2.38 0x34, 0x35?nr alarm threshold register (snr_alarm_th_low , snr_alarm_th_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.2.39 0x36, 0x37?ursor level register (cursor_level_low , cursor_level_high) . . . . . 60 3.2.40 0x38, 0x39?agc t arget register (dagc_target_low , dagc_target_high) . . . . . . 60 3.2.41 0x3a?ymbol detector modes register (detector_modes) . . . . . . . . . . . . . . . . 61 3.2.42 0x3b?eak detector delay register (peak_detector_delay) . . . . . . . . . . . . . . . . 62 3.2.43 0x3c?igital agc modes register (dagc_modes) . . . . . . . . . . . . . . . . . . . . . . . 62 3.2.44 0x3d?eed for ward equalizer modes register (ffe_modes) . . . . . . . . . . . . . . . . 63 3.2.45 0x3e?rror predictor modes register (ep_modes) . . . . . . . . . . . . . . . . . . . . . . 63 3.2.46 0x40, 0x41?hase detector meter register (pdm_low , pdm_high) . . . . . . . . . . 64 3.2.47 0x42?ver ow meter register (over ow_meter) . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.48 0x44, 0x45?c level meter register (dc_meter_low , dc_meter_high) . . . . . . . 64
t able of contents bt8960 single-chip 2b1q t ransceiver vi n8960dsb 3.2.49 0x46, 0x47?ignal level meter register (slm_low , slm_high) . . . . . . . . . . . . . . 65 3.2.50 0x48, 0x49?ar -end level meter register (felm_low , felm_high) . . . . . . . . . . . . 65 3.2.51 0x4a, 0x4b?oise level histogram meter register (noise_histogram_low , noise_histogram_high) . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.52 0x4c, 0x4d?it error rate meter register (ber_meter_low , ber_meter_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.2.53 0x4e?ymbol histogram meter register (symbol_histogram) . . . . . . . . . . . . . . 66 3.2.54 0x50, 0x51?oise level meter register (nlm_low , nlm_high) . . . . . . . . . . . . . . 66 3.2.55 0x5e, 0x5f?pll frequency register (pll_frequency_low , pll_frequency_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.2.56 0x70?ec read t ap select register (linear_ec_tap_select_read) . . . . . . . . . . . . 67 3.2.57 0x71?ec write t ap select register (linear_ec_tap_select_write) . . . . . . . . . . . 67 3.2.58 0x72?ec read t ap select register (nonlinear_ec_tap_select_read) . . . . . . . . 67 3.2.59 0x73?ec write t ap select register (nonlinear_ec_tap_select_write) . . . . . . . . 68 3.2.60 0x74?fe read t ap select register (dfe_tap_select_read) . . . . . . . . . . . . . . . . 68 3.2.61 0x75?fe write t ap select register (dfe_tap_select_write) . . . . . . . . . . . . . . . . 68 3.2.62 0x76?cratch pad read t ap select (sp_tap_select_read) . . . . . . . . . . . . . . . . . 68 3.2.63 0x77?cratch pad write t ap select (sp_tap_select_write) . . . . . . . . . . . . . . . . . 69 3.2.64 0x78?qualizer read select register (eq_add_read) . . . . . . . . . . . . . . . . . . . . . 69 3.2.65 0x79?qualizer write select register (eq_add_write) . . . . . . . . . . . . . . . . . . . . 70 3.2.66 0x7a?qualizer microcode read select register (eq_microcode_add_read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.2.67 0x7b?qualizer microcode write select register (eq_microcode_add_write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.2.68 0x7c?x7f?ccess data register (access_data_byte3:0) . . . . . . . . . . . . . . . . . 70 4.0 electrical & mechanical speci cations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4 clock t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.5 channel unit interface t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.6 microcomputer interface t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.6.1 t est and diagnostic inter face t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.6.2 analog speci cations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.6.3 t est conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.7 t iming measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.8 mechanical speci cations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
list of figures bt8960 single-chip 2b1q t ransceiver vii n8960dsb list of figures figure 1-1. 2b1q terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1-2. bt8960 detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 1-3. pcm6 voice pairgain block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 1-4. pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2-1. transmit section block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 2-2. first-order echo cancellation using the variable gain amplifier . . . . . . . . . . . . . . . . . . . 19 figure 2-3. receiver digital signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 2-4. digital front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 2-5. timing recovery and clock interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 2-6. serial sign-bit first mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 2-7. parallel master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 2-8. parallel slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 4-1. mclk timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 4-2. clock control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 4-3. channel unit interface timing, parallel master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 4-4. channel unit interface timing, parallel slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 4-5. channel unit interface timing, serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 4-6. mci write timing, intel mode (motel = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 4-7. mci write timing, motorola mode (motel = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 4-8. mci read timing, intel mode (motel = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 4-9. mci read timing, motorola mode (motel = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 4-10. internal write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 4-11. jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 4-12. smon timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 4-13. transmitted pulse template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 4-14. transmitter test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 4-15. standard output load (totem pole and three-state outputs) . . . . . . . . . . . . . . . . . . . . . 90 figure 4-16. open-drain output load ( irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 4-17. input waveforms for timing tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 4-18. output waveforms for timing tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 4-19. output waveforms for three-state enable and disable tests . . . . . . . . . . . . . . . . . . . . . . 92 figure 4-20. 100-pin plastic quad flat pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
list of figures bt8960 single-chip 2b1q t ransceiver viii n8960dsb
list of t ables bt8960 single-chip 2b1q t ransceiver ix n8960dsb list of tables t able 1-1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 t able 1-2. hardware signal de nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 t able 2-1. symbol sour ce selector/scrambler modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 t able 2-2. four -level bit-to-symbol conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 t able 2-3. t wo-level bit-to-symbol conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 t able 2-4. t wo-level symbol-to-bit conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 t able 2-5. four -level symbol-to-bit conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 t able 2-6. cr ystal oscillator cir cuit component v alues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 t able 2-7. t imers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 t able 2-8. device identi cation jt ag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 t able 3-1. register t able . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 t able 4-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 t able 4-2. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 t able 4-3. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 t able 4-4. external clock t iming requirements (mclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 t able 4-5. hclk switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 t able 4-6. symbol clock (qclk) switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 t able 4-7. channel unit inter face t iming requirements, parallel master mode . . . . . . . . . . . . . . . . 76 t able 4-8. channel unit inter face switching characteristics, parallel master mode . . . . . . . . . . . . . 76 t able 4-9. channel unit inter face t iming requirements, parallel slave mode . . . . . . . . . . . . . . . . . 77 t able 4-10. channel unit inter face switching characteristics, parallel slave mode . . . . . . . . . . . . . . 77 t able 4-11. channel unit inter face t iming requirements, serial mode . . . . . . . . . . . . . . . . . . . . . . . 78 t able 4-12. channel unit inter face switching characteristics, serial mode . . . . . . . . . . . . . . . . . . . . 78 t able 4-13. microcomputer inter face t iming requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 t able 4-14. microcomputer inter face switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 t able 4-15. t est and diagnostic inter face t iming requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 t able 4-16. t est and diagnostic inter face switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 84 t able 4-17. receiver analog requirements and speci cations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 t able 4-18. t ransmitter analog requirements and speci cations . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 t able 4-19. t ransmitted pulse t emplate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 t able 4-20. t ransmitter t est cir cuit component v alues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
list of t ables bt8960 single-chip 2b1q t ransceiver x n8960dsb
1 n8960dsb 1.0 system overview 1.1 functional summar y the bt8960 2b1q transcei v er is an inte gral component of rockwell's telecom- munications product line. the major b uilding blocks of a 2b1q terminal are sho wn in figure 1-1 . figure 1-1. 2b1q t erminal receive data transmit data framer/ channel unit bt8960 transceiver transformer and hybrid twisted pair
2 1.0 system over view 1.1 functional summar y bt8960 single-chip 2b1q t ransceiver n8960dsb the bt8960 comprises v e major functions: a transmit section, a recei v e sec- tion, a timing reco v ery and clock interf ace, a microcomputer interf ace, and a test and diagnostic interf ace. figure 1-2 details the connections within and between each of these functional blocks. figure 1-2. bt8960 detailed block diagram echo canceler timing recovery/ crystal amplifier diag- nostics jtag receive section microcomputer interface and system control transmit section tbclk motel ale cs rd/ds wr/r/w ad[7:0] irq rst txp txn rq[0]/bclk smon tms tdi tck tdo tq[1]/tdat tq[0] vga pll voltage reference generator pulse- shaping filter variable- line driver txpsn txpsp txldin txldip control and status registers timers micro- computer interface ready addr[7:0] rxp rxn rxbp rxbn muxed gain dac adc digital front end equalizer detector receive channel unit interface rq[1]/rdat rbclk hclk qclk xtali/mclk xtalo xout rbias vcomo vcomi vccap vrxp,vrxn vtxp,vtxn transmit channel unit interface symbol source/ scrambler
3 1.0 system over view 1.1 functional summar y bt8960 single-chip 2b1q t ransceiver n8960dsb 1.1.1 t ransmit section the source of transmitted symbols is programmable through the microcomputer interf ace. the primary choices include e xternal 2b1q-encoded data presented to the tq[1,0]/td a t pins of the channel unit interf ace, internally looped-back recei v e symbols from the detector , or a constant ?ll ones?source. the symbols are then optionally scrambled. isolated pulses can also be generated to support the testing of pulse templates. the digital symbols are transformed to an analog signal via the d a c, which is highly linear in order to maximize the echo cancellation and detection properties of the signal. in addition, the transmit po wer le v el of the d a c may be adjusted via the t ransmitter gain re gister [tx_g ain; 0x29] to optimize performance. the t ransmitter calibration re gister [tx_calibrate; 0x28] contains the nominal setting for the transmitter g ain which is calibrated and hard-coded at the f actory . the pulse-shaping lter then conditions the signal to pre v ent crosstalk to adjacent sub- scriber lines. finally , the dif ferential line dri v er pro vides the current dri ving capa- bilities and lo w-distortion characteristics needed to dri v e a lar ge range of subscriber lines at lo w-bit error rates. 1.1.2 receive section the dif ferential v ariable gain ampli er (v ga) recei v es the data from the sub- scriber line. balancing inputs (rxbp , rxbn) are pro vided to accommodate rst- order transmit echo cancellation via an e xternal h ybrid. the g ain is programma- ble so that the dynamic range of the analog-to-digital con v erter (adc) can be maximized according to the attenuation of the subscriber line. digitized recei v e data is passed to the digital signal processor (dsp) portion of the bt8960. after dc of fset cancellation, a replica of the transmit signal is sub- tracted from the total recei v e signal by a digital echo canceler . the resultant f ar - end signal is then conditioned by an equalization stage consisting of automatic gain control (a gc), a feed-forw ard equalizer , a decision-feedback equalizer , and an error predictor . a mode-dependent detector is then used to reco v er the 2b1q-encoded data from the equalized signal. the channel unit interf ace then pro vides an optional descrambling function follo wed by parallel or serial output of the sign and magnitude bits on pins rq[1,0]/rd a t . a number of meters are implemented within the recei v er to pro vide a v erage le v el indications at v arious points in the recei v e signal path. the recei v e section also performs remote unit clock reco v ery through an on-chip phase lock loop (pll) circuit. 1.1.3 t iming recover y and clock interface the clock interf ace includes a crystal ampli er module to reduce the e xternal components needed for clock generation. the crystal frequenc y must be 64 times the desired symbol rate. when con gured as a remote unit, the pll module reco v ers the incoming data clock and outputs it on the qclk pin (and also the bclk pin for serial mode operation). the hclk output, which is synchronized to the qclk signal, can be con gured to c ycle at 16, 32, or 64 times the symbol rate.
4 1.0 system over view 1.1 functional summar y bt8960 single-chip 2b1q t ransceiver n8960dsb 1.1.4 microcomputer interface the microcomputer interf ace (mci) pro vides access to a 256-byte address space within the transcei v er . a combination of direct and indirect addressing methods are used to access all internal locations. the mci is designed to interf ace with both intel- and motorola-style processors with no additional glue logic. a mo tel control pin is pro vided to con gure the b us interf ace control/handshak e lines to conform to common motorola/intel con v entions. a muxed control pin is pro vided to con gure the b us interf ace address and data lines for multiple x ed or independent data/address b us operation. little-endian data formatting (least sig- ni cant byte of a multibyte w ord stored at the lo west byte-address location) is used in all cases, re g ardless of mo tel pin selection. a read y control pin is pro vided to support w ait-state insertion. an interrupt request (irq) output pin supports lo w-latenc y responses to time-critical e v ents within the transcei v er . eight 16-bit timers and ten measurement meters are inte grated into the trans- cei v er . the timers support v arious metering functions within the recei v er section, and of f-load the e xternal microcomputer from comple x timing operations associ- ated with startup procedures. control and monitoring access to the timers and meters is pro vided through the microcomputer interf ace. 1.1.5 t est and diagnostic interface (jt ag) the test and diagnostic interf ace comprises a test access port and a serial monitor output (smon). the test access port conforms to ieee std 1149.1-1990 , ( ieee standard t est access port and boundary scan architecture). also referred to as joint t est action group (jt a g), this interf ace pro vides direct serial access to each of the transcei v er s i/o pins. this capability can be used during an in-circuit board test to increase the testability and reduce the cost of the in-circuit test pro- cess. the serial monitor output can be vie wed as a real-time virtual probe for look- ing at the transcei v er s internal signals. the programmable signal source is shifted out serially at 16 times the symbol rate. the majority of the recei v e signal path is accessible through this output.
5 1.0 system over view 1.2 applications bt8960 single-chip 2b1q t ransceiver n8960dsb 1.2 applications 1.2.1 v oice/data pairgain a well-established mark et e xists for v oice pair g ain systems. these systems trans- port se v eral simultaneous phone con v ersations o v er a single twisted pair . the y are used by telecommunications service pro viders to maximize the utilization of the e xisting copper plant, and allo w it to pro vision man y more telephone circuits than possible with ordinary 4 khz analog transport. the e xternal interf aces of v oice pair g ain systems, at both the central of ce and remote ends, are analog po ts lines. v arious carrier techniques e xist to f acilitate the single-pair transmission such as: the frequenc y domain multiple x ed (fdm) systems and t ime domain multiple x ed (tdm) systems. in fdm systems, each v oice channel is modulated by a successi v ely higher carrier , therefore the com- posite transmission consists of se v eral frequenc y bands. in tdm systems, the v oice data is digitized and sampled in a channel-multiple x ed f ashion. although fdm systems are currently elded, recent trends are clearly to w ard tdm systems due to the inherent adv antages associated with digital transmission. t raditional 1 + 3, also called pcm4 v oice pair g ain systems, use a combina- tion of 2:1 adpcm compression and basic rate isdn u-interf ace de vices to transport four v oice con v ersations on one twisted pair . the disadv antage of this scheme is that clear 64 kbps channel capacity is lost due to the adpcm v oice compression algorithm. this may pre v ent high-speed f acsimile transmissions from being transported reliably . re g arding the bt8960, an alternate w ay e xists to implement this type of v oice pair g ain equipment. a bt8960-based system can transport four or six clear 64 kbps channels on a single pair . clear 64 kbps trans- port assures the transmission of an y baud-rate f acsimile or can be used to pro vi- sion special data services such as switched 56, clear 64, and frame relay . figure 1-3 sho ws the architecture of a pcm6 v oice pair g ain system. as illus- trated, six analog subscriber line interf ace cards (slic) are connected to a con- centrating framer . the function of this framer is to time-multiple x the pcm data from the slics, create a transport frame, and handle signaling information. the output of the framer is then passed on to the bt8960 for con v ersion into the 2b1q code suitable for long-reach transport o v er the loop plant.
6 1.0 system over view 1.2 applications bt8960 single-chip 2b1q t ransceiver n8960dsb 1.2.2 internet connectivity t ransport the gro wth of the internet has created a tremendous demand for additional band- width in the local loop. when e xisting loop f acilities are used to pro vide connec- ti vity to internet serv ers, the y are limited to the 128 kbps of fered by basic rate isdn (bri) service. although those same loops could be pro visioned through hdsl (for e1 or t1 transport rates), the tarif f structure for these services puts their bandwidth be yond the practical reach of most consumers. it is unlik ely that the e1/t1 tarif f structure will change soon since it still represents signi cant v alue for b usiness customers using e1/t1 leased lines for corporate data and v oice e xchange. the 128 kbps rate of fered by bri is suf cient for the te xt and graphic content of most of today's home pages. ho we v er , when motion, video, or interacti vity are added, the data rate required is increased to well o v er 300 kbps. the adv ent of the bt8960 creates an intermediate solution between bri and e1/t1 which opens a host of lo w-cost, higher bandwidth possibilities. w ith the bt8960, local loops could be pro visioned for data rates up to 384 kbps with lo w- cost hardw are. in addition, the full isdn 18,000 ft. carrier service area could be serv ed with a higher data rate. enabling hardw are could, for e xample, tak e the form of lan e xtender equipment, and terminals for such equipment could ha v e standard ethernet connections to routers, personal computers, or w orkstations. the terminals could also use the bt8960 2b1q transport mechanism for the local loop link to the central of ce or internet serv er location. by placing a slic in the terminal and reserving a 64 kbps channel for v oice transport, simultaneous data and v oice service could be of fered o v er a single twisted pair . the e xtraordinary lo w po wer of the bt8960 allo ws for customer site equipment to be remotely po wered, thereby guaranteeing lifeline po ts service in the e v ent of po wer loss at the customer site. figure 1-3. pcm6 v oice pairgain block diagram slic slic slic slic slic slic pcm f r amer bt8960 local loop
7 1.0 system over view 1.2 applications bt8960 single-chip 2b1q t ransceiver n8960dsb 1.2.3 isdn basic rate interface concentrator since man y telecommunications service pro viders are positioning bri service as residential internet or telecommuter connecti vity , the lack of installed copper pairs into the residence could be a serious limitation to the proliferation of the ser - vice. the bt8960 solv es this problem because it is capable of 416 kbps data rates. thus, it enables the transport of tw o full bri u-interf ace channels (4b + 2d) on a single twisted pair . alternati v ely , a bri service and tw o po ts lines can be pro visioned o v er a single twisted pair . another possible combination is six b-channels with a consol- idated d-channel for the pro visioning of three isdn lines on a single twisted pair . users of this equipment can include a small of ce with tw o computers, each needing bri service, or a residence requiring a bri line and tw o po ts lines. the primary adv antage of (1 or 2 bris + 1 or 2 po ts) is there is no need for e xpen- si v e digital phones and when a po ts function is used, the full bri bandwidth for data traf c is retained.
8 1.0 system over view 1.3 pin descriptions bt8960 single-chip 2b1q t ransceiver n8960dsb 1.3 pin descriptions the bt8960 is packaged in a 100-pin plastic quad flat p ack (pqfp). the pin assignments are sho wn in figure 1-4 . a listing of pin labels, numbers, and i/o assignments is gi v en in t able 1-1 . signal de nitions are pro vided in t able 1-2 . the coding used in the i/o column is: o = digital output, o a = analog output, od = open-drain output, i = digital input, ia = analog input, and i/o = bidirectional. figure 1-4. pin diagram 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 vdd1 cs rd / ds wr /r/ w ale irq read y ad[0] ad[1] ad[2] ad[3] ad[4] ad[5] ad[6] dgnd dgnd vdd2 ad[7] mo tel muxed addr[7] addr[6] addr[5] addr[4] addr[3] addr[2] addr[1] addr[0] smon vdd1 rxbn rxbp rxn rxp a gnd a gnd txn a gnd v aa txp txldin txldip txpsn txpsp a test2 a test1 v aa v aa a gnd vtxn vtxp vccap vcomo vcomi rbias v aa v aa a gnd vrxn vrxp dgnd dgnd vdd2 rst hclk xout dgnd vdd1 xt alo xt ali/mclk vdd2 dgnd dtest1 dtest2 dtest3 vdd1 dgnd dtest4 a gnd a gnd 53 52 51 80 1 dgnd dgnd vdd2 tck tms tdi tdo dtest6 dtest5 tbclk rbclk rq[0]/bclk rq[1]/rd a t qclk tq[0] tq[1]/td a t dgnd vdd1 a gnd v aa bt8960 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
9 1.0 system over view 1.3 pin descriptions bt8960 single-chip 2b1q t ransceiver n8960dsb t able 1-1. pin descriptions pin pin label i/o pin pin label i/o pin pin label i/o pin pin label i/o 1 vdd1 26 addr[2] i 51 vrxp oa 76 agnd 2 cs i 27 addr[1] i 52 vrxn oa 77 rxp ia 3 rd/ds i 28 addr[0] i 53 agnd 78 rxn ia 4 wr/r/w i 29 smon o 54 v aa 79 rxbp ia 5 ale i 30 vdd1 55 v aa 80 rxbn ia 6 irq od 31 dgnd 56 rbias oa 81 v aa 7 ready od 32 dgnd 57 vcomi oa 82 agnd 8 ad[0] i/o 33 vdd2 58 vcomo oa 83 vdd1 9 ad[1] i/o 34 rst i 59 vccap oa 84 dgnd 10 ad[2] i/o 35 hclk o 60 vtxp oa 85 tq[1]/tda t i 11 ad[3] i/o 36 xout o 61 vtxn oa 86 tq[0] i 12 ad[4] i/o 37 dgnd 62 agnd 87 qclk o 13 ad[5] i/o 38 vdd1 63 v aa 88 rq[1]/rda t o 14 ad[6] i/o 39 xt alo o 64 v aa 89 rq[0]/bclk o 15 dgnd 40 xt ali/mclk i 65 a test1 ia 90 rbclk i 16 dgnd 41 vdd2 66 a test2 ia 91 tbclk i 17 vdd2 42 dgnd 67 txpsp oa 92 dtest5 i 18 ad[7] i/o 43 dtest1 i 68 txpsn oa 93 dtest6 i 19 mo tel i 44 dtest2 i 69 txldip ia 94 tdo o 20 muxed i 45 dtest3 i 70 txldin ia 95 tdi i 21 addr[7] i 46 vdd1 71 txp oa 96 tms i 22 addr[6] i 47 dgnd 72 v aa 97 tck i 23 addr[5] i 48 dtest4 i 73 agnd 98 vdd2 24 addr[4] i 49 agnd 74 txn oa 99 dgnd 25 addr[3] i 50 agnd 75 agnd 100 dgnd
10 1.0 system over view 1.3 pin descriptions bt8960 single-chip 2b1q t ransceiver n8960dsb t able 1-2. hardware signal de nitions (1 of 4) pin label signal name i/o definition microcomputer interface (mci) mo tel motorola/ intel i selects between motorola and intel handshake conventions for the rd / ds and wr /r/ w signals. mo tel = 1 for motorola protocol: ds , r/ w mo tel = 0 for intel protocol: rd , wr ale address latch enable i falling-edge-sensitive input. the value of ad[7:0] when muxed = 1, or addr[7:0] when muxed = 0, is internally latched on the falling edge of ale. cs chip select i active-low input used to enable read/write operations on the microcomputer inter face (mci). rd / ds read / data strobe i bimodal input for controlling read/write access on the mci. when mo tel = 1 and cs = 0, rd / ds behaves as an active-low data strobe ds . internal data is output on ad[7:0] when ds = 0 and r/ w = 1. external data is internally latched from ad[7:0] on the rising edge of ds when r/ w = 0. when mo tel = 0 and cs = 0, rd / ds behaves as an active-low read strobe rd . internal data is output on ad[7:0] when rd = 0. write operations are not controlled by rd in this mode. wr / r/ w write / read/ write i bimodal input for controlling read/write access on the mci. when mo tel = 1 and cs = 0, wr /r/ w behaves as a read/write select line r/ w . internal data is output on ad[7:0] when ds = 0 and r/ w = 1. external data is internally latched from ad[7:0] on the rising edge of ds when r/ w = 0. when mo tel = 0 and cs = 0, wr /r/ w behaves as an active-low write strobe wr . external data is internally latched from ad[7:0] on the rising edge of wr . read operations are not controlled by wr in this mode. ad[7:0] address- data[7:0] i/o 8-bit bidirectional multiplexed address-data bus. ad[7] = msb, ad[0] = lsb. usage is controlled using the muxed signal as de ned below . addr[7:0] address bus[7:0] (not multiplexed) i provides a glueless inter face to microcomputers with separate address and data buses. addr[7] = msb, addr[0] = lsb. usage is controlled using the muxed signal. muxed addressing mode select i controls the mci addressing mode. when muxed = 1, the mci uses ad[7:0] as a multiplexed signal for address and data (typical of intel processors). when muxed = 0, the mci uses addr[7:0] as the address input and ad[7:0] for data only (typical of motorola processors). ready ready od active-low , open-drain output that indicates that the mci is ready to transfer data. can be used to signal the microcomputer to insert wait states. irq interrupt request od active-low , open-drain output that indicates requests for interrupt. asserted whenever at least one unmasked interrupt ag is set. remains inactive whenever no unmasked interrupt ags are present. rst reset i asynchronous, active-low , level-sensitive input that places the transceiver in an inactive state by setting the power -down mode bit of the global modes and sta- tus register [global_modes; 0x00], and zeroing the clk_freq[1,0] bits of the pll modes register [pll_modes; 0x22], and the hclk_freq[1,0] bits of the serial monitor sour ce select register [serial_monitor_sour ce; 0x01]. all ram con- tents are lost. does not affect the state of the test access port which is reset automatically at power -up only .
11 1.0 system over view 1.3 pin descriptions bt8960 single-chip 2b1q t ransceiver n8960dsb channel unit interface rq[1]/ rda t rq[0]/ bclk receive quat 1/ receive data receive quat 0/ bit clock o o rq[1]/rda t and rq[0]/bclk are bimodal outputs that represent the sign and magnitude bits of the received quaternar y output symbol in parallel channel unit modes (rq[1], rq[0]), and the serial-data and bit-clock outputs in serial chan- nel unit modes (rda t , bclk). behavior of these outputs is con gurable through the channel unit inter face modes register [cu_inter face_modes; 0x06] for par - allel master , parallel slave, serial magnitude-bit- rst and serial sign-bit- rst operations. for parallel mode operation: rq[1] = sign bit output rq[0] = magnitude bit output both outputs are updated at the symbol rate on the rising edge of qclk (master mode) or the rising/falling edge (programmable) of rbclk (slave mode). for serial mode operation: rda t = serial quaternar y data output bclk = bit-rate (two times symbol rate) clock output rda t is updated at the bit rate on the rising edge of bclk tq[1]/ tda t tq[0] t ransmit quat 1/ t ransmit data t ransmit quat 0 i i tq[1]/tda t and tq[0] are bimodal inputs that represent the sign and magnitude bits of the quaternar y input symbol to be transmitted in parallel channel unit modes (tq[1], tq[0]), and the serial data input in serial channel unit modes (tda t). interpretation of these inputs is con gurable through the channel unit inter face modes register [cu_inter face_modes; 0x06] for parallel master , par - allel slave, serial magnitude-bit- rst and serial sign-bit- rst operations. for parallel mode operation: tq[1] = sign bit input tq[0] = magnitude bit input both inputs are sampled at the symbol rate on the falling edge of qclk (mas- ter mode) or the rising/falling edge (programmable) of tbclk (slave mode). for serial mode operation: tda t = serial quaternar y data input tq0 = don? care (tie or pull up to supply rail) tda t is sampled at the bit rate (two times the symbol rate) on the falling edge of bclk. qclk quaternar y clock o runs at the symbol rate. it de nes the data on the tq and rq inter faces. qclk is also used to frame transmit/receive quats in serial mode. tbclk t ransmit baud- rate clock i functions as the transmit baud-rate clock input. it must be frequency locked to qclk. this input is used only when the channel unit inter face is in parallel slave mode. if it is unused, it should be tied to vdd2 or dgnd. rbclk receive baud- rate clock i functions as the receive baud-rate clock input. it must be frequency locked to qclk. this input is used only when the channel unit inter face is in parallel slave mode. if it is unused, it should be tied to vdd2 or dgnd. t able 1-2. hardware signal de nitions (2 of 4) pin label signal name i/o definition
12 1.0 system over view 1.3 pin descriptions bt8960 single-chip 2b1q t ransceiver n8960dsb analog transmit interface txp , txn t ransmit positive, negative oa differential t ransmit line driver outputs. these signals are used to drive the subscriber line after passing through the hybrid and line transformer . txldip , txldin t ransmit line driver in positive, negative ia differential t ransmit line driver inputs. these inputs should be connected to the txpsp , txpsn outputs after passing through an external rc lter . txpsp , txpsn t ransmit pulse- shaping filter positive, negative oa differential t ransmit pulse-shaping filter outputs. these outputs should be con- nected to an external rc lter , which is then connected to the txldip and txl- din inputs. analog receive interface rxp , rxn receive positive, negative ia differential receiver inputs. rxp and rxn receive the signal from the subscriber line. rxbp , rxbn receive balance positive, negative ia differential receiver balance inputs. rxbp and rxbn are used to subtract the echo of the signal being transmitted on the subscriber line. they should be con- nected to the txp , txn output pins through the hybrid cir cuit. this signal is sub- tracted from the signal being received by the rxp and rxn inputs in the v ariable gain ampli er (vga). voltage reference generator interface rbias resistor bias oa connection point for external bias resistor . vcomo common mode v oltage outputs oa common mode voltage for the analog cir cuitr y . this pin should be connected to an external ltering capacitor . vcomi common mode v oltage inputs oa common mode voltage for the analog cir cuitr y . this pin should be connected to an external ltering capacitor . vccap v oltage compen- sation capacitor oa analog v oltage compensation capacitor . this pin should be connected to an external ltering capacitor . vrxp , vrxn receiver v oltage reference posi- tive, negative oa analog receive cir cuitr y reference v oltages. these pins should be connected to external ltering capacitors. vtxp , vtxn t ransmit v oltage reference posi- tive, negative oa analog t ransmit cir cuitr y reference v oltages. these pins should be connected to external ltering capacitors. clock interface xt ali/ mclk cr ystal in/master clock i a bimodal input that can be used as the cr ystal input or as the master clock input. if an external clock is connected to this input, xt alo should be left oat- ing. the frequency of the cr ystal or clock should be 64 times the symbol rate (32 times the data rate). xt alo cr ystal output o connection point for the cr ystal. hclk high speed clock out o hclk can be con gured to run at 16, 32, or 64 times the symbol rate. upon reset, it is set to 64 times the symbol rate. this clock will be phase locked to the incoming data when the bt8960 is con gured as the remote unit. xout cr ystal clock out o buffered-cr ystal oscillator output. t able 1-2. hardware signal de nitions (3 of 4) pin label signal name i/o definition
13 1.0 system over view 1.3 pin descriptions bt8960 single-chip 2b1q t ransceiver n8960dsb test and diagnostic interface tdi jt ag t est data input i jt ag test data input per ieee std 1149.1-1990. used for loading all serial instructions and data into internal test logic. sampled on the rising edge of tck. tdi can be left unconnected if it is not being used because it is pulled-up inter - nally . tms jt ag t est mode select i jt ag test mode select input per ieee std 1149.1-1990. internally pulled-up input signal used to control the test-logic state machine. sampled on the rising edge of tck. tms can be left unconnected if it is not being used because it is pulled-up internally . tdo jt ag t est data output o jt ag test data output per ieee std 1149.1-1990. three-state output used for reading all serial con guration and test data from internal test logic. updated on the falling edge of tck. tck jt ag t est clock input i jt ag test clock input per ieee std 1149.1-1990. used for all test inter face and internal test logic operations. if unused, tck should be pulled low . smon serial monitor o serial data output used for real-time monitoring of internal signal-path registers. the sour ce register is selected through the serial monitor sour ce select regis- ter [serial_monitor_sour ce; 0x01]. 16-bit words are shifted out, lsb rst, at 16 times the symbol rate. the rising edge of qclk de nes the start least signi - cant bit (lsb) of each word. the output is updated on the rising edge of an inter - nal clock running at 16 times qclk. dtest[1:4] digital t ests 1? i active-high test inputs used by rockwell to enable internal test modes. these inputs should be tied to digital ground (dgnd). dtest[5, 6] digital t est 5, 6 i active-low test inputs used by rockwell to enable internal test modes. these inputs should be tied to the i/o buffer power supply (vdd2). a test[1,2] analog t est 1, 2 ia analog test inputs used by rockwell for internal test modes. these inputs should be left oating (no connect, nc). power and ground vdd1 core logic power supply dedicated supply pins powering the digital core logic functions. vdd2 i/o buffer power supply dedicated supply pins powering the digital i/o buffers. dgnd digital ground dedicated ground pins for the digital cir cuitr y . must be held at same potential as agnd. v aa analog power supply dedicated supply pins powering the analog cir cuitr y . agnd analog ground dedicated ground pins for the analog cir cuitr y . must be held at the same poten- tial as dgnd. t able 1-2. hardware signal de nitions (4 of 4) pin label signal name i/o definition
14 1.0 system over view 1.3 pin descriptions bt8960 single-chip 2b1q t ransceiver n8960dsb
15 n8960dsb 2.0 functional description 2.1 t ransmit section the transmit section is illustrated in figure 2-1 . it comprises four major func- tions: a symbol source selector/scrambler , a v ariable g ain digital-to-analog con- v erter (d a c), a pulse-shaping lter , and a line dri v er . figure 2-1. t ransmit section block diagram transmit channel unit interface symbol variable-gain line driver control registers external rc filter tq[1,0] txp txn isolated pulses detector loopback ones (1s) source/ scrambler pulse- shaping filter dac
16 2.0 functional description 2.1 t ransmit section bt8960 single-chip 2b1q t ransceiver n8960dsb 2.1.1 symbol source selector/scrambler the input source selector/scrambler can be con gured through the t ransmitter modes re gister [transmitter_modes; 0x0b] data_source [2:0] bits to select the source of the data to be transmitted and determine whether or not the data is scrambled. the symbol source selector/scrambler modes are speci ed in t able 2- 1 . t able 2-1. symbol source selector/scrambler modes data_source[2:0] symbol source selector/scrambler mode 000 isolated pulse. level selected by isolated_pulse[1,0]. the meter timer must be enabled and in the con- tinuous mode. the pulse repetition inter val is determined by the meter -timer -countdown inter val. 001 four -level scrambled detector loopback. sign and magnitude bits from the receiver detector are scram- bled and looped back to the transmitter . feedback polynomial determined by the htur_lfsr control bit. 010 four -level unscrambled data. t ransmits the four -level (2b1q) sign and magnitude bits from the transmit channel unit. 011 four -level scrambled ones. t ransmits a scrambled, constant high-logic level as a four -level (2b1q) sig- nal. feedback polynomial determined by the htur_lfsr control bit. 100 reser ved. 101 four -level scrambled data. scrambles and transmits the four -level (2b1q) sign and magnitude bits from the channel unit transmit inter face. feedback polynomial determined by the htur_lfsr control bit. 110 t wo-level unscrambled data. constantly for ces the magnitude bit from the transmit channel unit inter - face to a logic zero, and transmits the resulting two-level signal (as determined by the sign bit) without scrambling. v alid output levels limited to +3, ?. 111 t wo-level scrambled ones. t ransmits a scrambled, constant high-logic level, as a two-level signal. feed- back polynomial determined by the htur_lfsr control bit. scrambler is run at the symbol rate (half-bit rate) to produce the sign bit of the transmitted signal while the magnitude bit is sour ced with a constant logic zero. v alid output levels limited to +3, ?.
17 2.0 functional description 2.1 t ransmit section bt8960 single-chip 2b1q t ransceiver n8960dsb the bit stream is con v erted into symbols for the four -le v el cases as sho wn in t able 2-2 . in tw o-le v el mode, the magnitude bit is forced to a zero. this forces the sym- bols to be +3 and ?, as sho wn in t able 2-3 . the scrambler is essentially a 23- bit-long linear feedback shift re gister (lfsr). the feedback points are programmable for central of ce and remote ter - minal applications using the htur_lfsr bit of the t ransmitter modes re gister . the lfsr polynomials for local (htu-c/l tu) and remote (htu-r/ntu) unit oper - ations are: the scrambler operates dif ferently depending on whether a tw o-le v el or four - le v el mode is speci ed. in 2-le v el scrambled-ones mode, the lfsr is clock ed once-per -symbol; in 4-le v el mode, the lfsr is clock ed twice-per -symbol. the t ransmitter modes re gister can also be used to zero the output of the transmitter using the transmitter_of f control bit. the bt8960 can generate isolated pulses to support the testing of pulse tem- plates. when in the isolated pulse mode, the output consists of a single pulse sur - rounded by zeros. note: zero is not a v alid 2b1q le v el and only occurs in this special mode or when the transmitter is of f. the repetition rate of the pulses is controlled by the meter timer . an y of the four 2b1q le v els may be chosen via the t ransmitter modes re gister s isolated_pulse[1,0] control bits. t able 2-2. four -level bit-to-symbol conversions first input bit (sign) second input bit (magnitude) output symbol 0 0 ? 0 1 ? 1 1 +1 1 0 +3 t able 2-3. t wo-level bit-to-symbol conversions first input bit (sign) second input bit (magnitude) output symbol 0 don? care ? 1 don? care +3 l o c a l x 23 x 5 1 ? ? t r e m o t e x 23 x 18 1 ? ? t
18 2.0 functional description 2.1 t ransmit section bt8960 single-chip 2b1q t ransceiver n8960dsb 2.1.2 v ariable gain digital-to-analog converter a four -le v el digital-to-analog con v erter (d a c) is inte grated into the bt8960 to accurately con v ert the output of the symbol source to analog form. the normal- ized v alues of these four analog le v els are: +3, +1, ? and ?. each represents a symbol or quat. t o pro vide precise adjustment of the transmitted po wer , the le v el of the d a c may be adjusted. the t ransmitter gain re gister [tx_g ain; 0x29] sets the le v el. during the manuf acturing of the bt8960, one source of v ariation in the trans- mitter le v els is process v ariations. the t ransmitter calibration re gister [tx_calibrate; 0x28] contains a read-only v alue which nulls this v ariation. the v alue of this re gister is determined for each bt8960 de vice during production test- ing. upon initialization, the t ransmitter gain re gister should be loaded based on the t ransmitter calibration re gister . if there are other sources of transmit po wer v ariation (e.g., a nonstandard h ybrid or attenuati v e lightening protection), the transmitter g ain must be adjusted to include these af fects. 2.1.3 pulse-shaping filter the pulse-shaping lter lters the quats output from the v ariable-g ain d a c. this lter , when combined with other ltering in the signal path, produces a transmit- ted signal on the line that meets the po wer spectral density , transmitted po wer , and pulse-shaping requirements, as speci ed in the electrical speci cations sec- tion of this datasheet. 2.1.4 line driver the line dri v er b uf fers the output of the pulse-shaping lter to dri v e di v erse loads. the output of the line dri v er is dif ferential.
19 2.0 functional description 2.2 receive section bt8960 single-chip 2b1q t ransceiver n8960dsb 2.2 receive section lik e the transmit section, the recei v e section consists of both analog and digital circuitry . the v ga pro vides the interf ace to the analog signals recei v ed from the line and the h ybrid. the analog-to-digital con v erter (adc) then digitizes the analog signal so it can be further processed in the digital signal processing (dsp) section of the recei v er . the recei v er dsp section includes: front-end processing, echo cancellation, equalization, and symbol detection. 2.2.1 v ariable gain ampli er the v ariable gain ampli er (v ga) has tw o purposes. the rst is to pro vide a dual-dif ferential analog input so the pseudo-transmit signal created by the h ybrid can be subtracted from the signal from the line transformer . this subtraction pro- vides rst-order echo cancellation, which results in a rst-order approximation of the signal recei v ed from the line. figure 2-1 illustrates the recommended sug- gested echo-cancellation circuit interconnections. all of f-chip circuitry , including the h ybrid and anti-alias lters, consists entirely of passi v e components. further echo cancellation occurs in the recei v er dsp . the second purpose of the v ga is to pro vide programmable g ain of the recei v ed signal prior to passing it to the adc. this reduces the resolution required for the adc. there are six g ain settings ranging from 0 db to 15 db. the g ain is controlled via the g ain[2:0] control bits in the adc control re gister [adc_control; 0x21]. see the re gisters section of this datasheet for a more detailed description of the g ain[2:0] control bits. figure 2-2. first-order echo cancellation using the v ariable gain ampli er rxp rxn rxbp rxbn txp txn line (twisted pair) to adc on-chip circuitry off-chip circuitry line impedance matching gain[2:0] anti-alias filter hybrid + anti-alias filter + + + + line driver line transformer + resistors
20 2.0 functional description 2.2 receive section bt8960 single-chip 2b1q t ransceiver n8960dsb 2.2.2 analog-to-digital converter the adc pro vides 16 bits of resolution. the analog input from the v ariable g ain ampli er is con v erted into digital data and output at the symbol rate. 2.2.3 digital signal processor the digital signal processor (dsp) includes v e least mean squared (lms) l- ters: an echo canceller (ec), a digital automatic gain controller (d a gc), a feed f orw ard equalizer (ffe), an error predictor (ep), and a decision feedback equalizer (dfe). these lters are used to equalize the recei v ed signal so that the symbols transmitted from the f ar -end can be reliably reco v ered. the dsp uses symbol rate sampling for all processing functions. their interconnections and relationships to the digital front-end and the detector are illustrated in figure 2-3 . figure 2-3. receiver digital signal processing digital f ront-end channel unit interf ace echo canceller t r ansmit symbol equaliz er dfe detector lec d a gc ffe nec ep pkd slicer
21 2.0 functional description 2.2 receive section bt8960 single-chip 2b1q t ransceiver n8960dsb 2.2.3.1 digital front-end prior to the main signal processing, the input signal must be adjusted for an y dc of fset. the front-end module also monitors the input signal le v el, which includes measuring dc and a c input signal le v els, detecting and counting o v er o ws, and detecting alarms based on the f ar -end signal le v el. figure 2-4 summarizes the fea- tures of the digital front-end module. figure 2-4. digital front-end block diagram echo-f ree signal from nec dc offset from mci accum ulator result register f ar-end le v el meter compar ator compar ator f ar-end alar ms high threshold from mci lo w threshold from mci high_f elm interr upt lo w_f elm interr upt result register accum ulator dc le v el meter accum ulator absolute result register signal le v el meter adc data r , t o ec + ov er o w detector counter result register ov er o w monitor ov er o w absolute v alue v alue
22 2.0 functional description 2.2 receive section bt8960 single-chip 2b1q t ransceiver n8960dsb 2.2.3.2 offset adjustment a nonzero dc le v el on the input can be corrected by a dc of fset v alue [dc_of fset_lo w , dc_of fset_high; 0x26, 0x27] which is subtracted from the input. the dc of fset is a 16- bit number and is programmed via the microcomputer interf ace. 2.2.3.3 dc level meter the dc le v el meter pro vides the monitoring needed for adapti v e of fset compen- sation. the of fset-adjusted input signal is accumulated o v er the meter timer inter - v al [meter_lo w , meter_high; 0x18, 0x19]. the 16 msbs are placed into the dc le v el meter re gisters [dc_meter_lo w , dc_meter_high; 0x44, 0x45]. 2.2.3.4 signal level meter the signal le v el meter pro vides the monitoring needed for adjusting the analog g ain circuit located prior to the adc. this v alue is accumulated o v er the meter timer interv al [meter_lo w , meter_high; 0x18, 0x19]. the 16 msbs are placed in the signal le v el meter re gisters [slm_lo w , slm_high; 1; 0x46, 0x47]. 2.2.3.5 over ow detection and monitoring the o v er o w sensor detects adc o v er o ws. the o v er o w monitor counts the number of o v er o ws, as indicated by the o v er o w sensor during the meter timer interv al [meter_lo w , meter_high; 0x18, 0x19]. the counter is limited to 8 bits. in the case of 256 or more o v er o ws during the measurement interv al, the counter will hold at 255. the counter is loaded into the ov er o w meter re gister [o v er o w_meter; 0x42] at the end of each measurement interv al. 2.2.3.6 far -end level meter the f ar -end le v el meter monitors the output of the echo canceler . since the echo canceler output had the echo of the transmitted signal subtracted from it, it is called the f ar -end signal. this v alue is accumulated o v er the meter timer interv al [meter_lo w , meter_high; 0x18, 0x19]. the 16 msbs are placed into the f ar -end le v el meter re gister [felm_lo w , felm_high; 0x48, 0x49]. 2.2.3.7 far -end level alarm the result of the f ar -end le v el meter is compared to tw o thresholds. when e xceeded, an interrupt is sent to the microcomputer interf ace, if enabled. the threshold is determined by the v alue in the f ar -end high alarm threshold re gis- ters [f ar_end_high_alarm_th_lo w , f ar_end_high_alarm_th_high; 0x30, 0x31] and the f ar -end lo w alarm threshold re gisters [f ar_end_lo w_alarm_th_lo w , f ar_end_lo w_alarm_th_high; 0x32, 0x33]. the interrupts high_felm and lo w_felm, are bits 2 and 1, respecti v ely of the irq source re gister [irq_source; 0x05]. the interrupts high_felm and lo w_felm, can be mask ed by writing a one to bits 2 and 1, respecti v ely of the interrupt mask re gister high [mask_high_re g; 0x03].
23 2.0 functional description 2.2 receive section bt8960 single-chip 2b1q t ransceiver n8960dsb 2.2.4 echo canceler the ec remo v es images of the transmitted symbols from the recei v ed signal and consists of tw o blocks: a linear and nonlinear echo canceler . the or g anization of the blocks is displayed in figure 2-3 . 2.2.4.1 linear echo canceler (lec) the linear echo canceler (lec) is a con v entional lms finite impulse response (fir) lter , which remo v es linear images of the transmitted symbols from the recei v ed signal. it consists of a 60-tap fir lter with 32-bit linear adapted coef - cients. when enabled, the last data tap of the echo canceler is treated specially . this serv es to cancel an y dc of fset that may be present. a freeze coef cient mode may be speci ed via the microcomputer interf ace. this mode disables the coef cient updates only . a special mode e xists to zero all of the coef cients; it is also enabled through the microcomputer interf ace. an additional mode e xists to zero the output of the fir with no ef fect on the coef cients. it is also enabled through the microcomputer interf ace. indi vidual ec coef cients can be read and written through the microcomputer interf ace. adaptation should be frozen prior to reading or writing coef cients. 2.2.4.2 nonlinear echo canceler (nec) the nonlinear echo canceler (nec) reduces the residual echo po wer in the echo canceler output caused by nonlinear ef fects in the transmitter d a c, recei v er adc, analog h ybrid circuitry , or line cables. the delay of the transmit-symbol input to the nec can be speci ed via the microcomputer interf ace: nonlinear echo canceler mode re gister [nonlinear_ec_modes; 0x09]. this allo ws the nec to operate on the peak of the echo re g ardless of dif fering delays in the echo path. a freeze coef cient mode may be speci ed via the microcomputer interf ace. this mode disables the coef cient updates only . a special mode e xists to zero all of the coef cients; it is also enabled through the microcomputer interf ace. an additional mode e xists to zero the output of the look-up table with no ef fect on the coef cients. it is also enabled through the microcomputer interf ace. the 64, 14-bit, indi vidual nec coef cients can be read and written through the microcomputer interf ace. adaptation should be frozen prior to reading or writing coef cients. 2.2.5 equalizer f our lms lters are used in the equalizer to process the echo canceler output so that recei v ed symbols can be reliably reco v ered. the lters are a digital automatic g ain controller , a feed forw ard equalizer , an error predictor , and a decision feed- back equalizer . their interconnections are sho wn in figure 2-3 . 2.2.5.1 digital automatic gain control the d a gc scales the echo-free signal to the optimum magnitude for subsequent processing. its structure is that of an lms lter , b ut it is a de generate case since there is only one tap. a freeze coef cient mode may be speci ed via the microcomputer interf ace. this mode disables the coef cient update only . the d a gc g ain coef cient can be read or written through the microcomputer interf ace. adaptation should be frozen prior to reading or writing the coef cient.
24 2.0 functional description 2.2 receive section bt8960 single-chip 2b1q t ransceiver n8960dsb 2.2.5.2 feed for ward equalizer (ffe) the feed f orw ard equalizer (ffe) remo v es precursors from the recei v ed signal. the ffe may be operated in a special adapt last mode. in this mode, which is useful during startup, only the last coef cient is updated. the last coef cient is the one which is multiplied with the oldest data sample, (sample #7). a freeze coef cient mode may be speci ed via the microcomputer interf ace. this mode disables the coef cient updates only . a special mode e xists to zero all of the coef cients. it is also enabled through the microcomputer interf ace. indi- vidual ffe coef cients can be read and written through the microcomputer inter - f ace. adaptation should be frozen prior to reading or writing coef cients. 2.2.5.3 error predictor (ep) the error predictor (ep) impro v es the performance of the equalizer by prognosti- cating errors before the y occur . a freeze coef cient mode may be speci ed via the microcomputer interf ace. this mode disables the coef cient updates only . a special mode e xists to zero all of the coef cients; it is also enabled through the microcomputer interf ace. indi vidual ep coef cients can be read and written through the microcomputer interf ace. adaptation should be frozen prior to read- ing or writing coef cients. 2.2.5.4 decision feedback equalizer (dfe) the decision feedback equalizer (dfe) remo v es postcursors from the recei v ed signal. a freeze coef cient mode may be speci ed via the microcomputer inter - f ace. this mode disables the coef cient updates only . a zero coef cients mode e xists to zero all of the coef cients; it is also enabled through the microcomputer interf ace. a zero lter output mode e xists to zero the output of the fir with no ef fect on the coef cients. it is also enabled through the microcomputer interf ace. indi vidual dfe coef cients can be read and written through the microcomputer interf ace. adaptation should be frozen prior to reading or writing coef cients. 2.2.5.5 microcoding the d a gc, ffe, and ep lters are implemented using an internal micropro- grammable digital signal processor (dsp) optimized for lms lters. internal dsp micro-instructions are stored in an on-chip ram. this microcode ram is loaded after po werup through the microcomputer interf ace when the transcei v er is initialized. 2.2.6 detector the detector con v erts the equalized recei v ed signal into a 2b1q symbol and pro- duces tw o error signals used in adapting the recei v er equalizers. the signal detec- tion uses tw o sub-blocks, a slicer , and a peak detector . additionally , the detector contains a scrambler and bit error rate (ber) meter for use during the startup sequence. 2.2.6.1 slicer the slicer thresholds the equalized signal to produce a 2b1q symbol. the input to the slicer is the ffe output minus the dfe and ep outputs. the slicer can operate in tw o modes: tw o-le v el and four -le v el. in the tw o-le v el mode, used during the part of startup when the only transmitted symbols are +3 or ?, the slicer threshold is set at zero. when in four -le v el mode, the cursor le v el is speci ed via the microcomputer interf ace. it is a 16- bit, 2 s complement number , b ut must be positi v e and less than 0x2aaa for proper operation.
25 2.0 functional description 2.2 receive section bt8960 single-chip 2b1q t ransceiver n8960dsb 2.2.6.2 peak detector (pkd) the pkd is only used during the tw o-le v el transmission part of startup. it oper - ates on the echo-free signal. a signal is detected to be a +3, if it is higher than both of its neighbors, or a ?, if it is lo wer than both of its neighbors. if neither of the peak ed conditions e xists, the output of the slicer is used. 2.2.6.3 error signals the detector computes tw o error signals for use in the equalizer: a 16-bit slicer and a 16-bit equalizer . 2.2.6.4 scrambler module the scrambler may operate as either a scrambler or as a descrambler . the scram- bler block is used during the scrambled-ones part of the startup sequence. this pro vides an error -free signal for equalizer adaptation. this scrambler is essen- tially a 23- bit-long lfsr with feedback. the feedback point depends on whether the transcei v er is being used in a central-of ce or remote-terminal application. when operating as a descrambler , the input source is the detector output. the symbol is con v erted to a bit stream, as sho wn in t able 2-4 for the tw o-le v el case. the symbol is con v erted to a bit stream, as sho wn in t able 2-5 for the four - le v el case. t able 2-4. t wo-level symbol-to-bit conversion input symbol output bit ? 0 +3 1 t able 2-5. four -level symbol-to-bit conversion input symbol first output bit (sign) second output bit (magnitude) ? 0 0 ? 0 1 +1 1 1 +3 1 0
26 2.0 functional description 2.2 receive section bt8960 single-chip 2b1q t ransceiver n8960dsb the lfsr operates in the same w ay in both cases, e xcept in the tw o-le v el case it is clock ed once-per -symbol and in the four -le v el case it is clock ed twice-per - symbol. when operating as a scrambler , the lfsr must rst be lock ed to the f ar -end source. once lock ed, it is then able to replicate the f ar -end input sequence, when its input is held at all ones. the locking sequence is controlled internally , initiated through the microcomputer interf ace by setting the lfsr_lock bit of the detector_modes re gister . the locking sequence consists of the follo wing four steps: 1. operate the lfsr as a descrambler for 23 bits. 2. operate the lfsr as a scrambler for 127 bits. the sync detector is acti v e during this period. 3. go to step 1 if synchronization w as not achie v ed, otherwise continue to step 4. 4. send an interrupt to the microcomputer , if unmask ed, indicating successful locking and continue operating as a scrambler . the sequence continues until the lfsr_lock control bit is cleared by the micro- computer . 2.2.6.5 sync detector the sync detector compares the output of the scrambler with the output of the symbol detector . the number of equi v alent bits is accumulated for 128 compari- sons. the result is then compared to a scrambler synchronization threshold re g- ister [scr_sync_th; 0x2e], lock is declared, and the sync bit of the irq_source re gister is set if the count is greater than the threshold. f or a count less than or equal to the threshold, no lock condition is declared and the sync bit is unaf fected. 2.2.6.6 detector meters the detector consists of v e meters: a ber meter , a symbol histogrammer , a noise-le v el meter , a noise-le v el histogram meter , and an snr alarm meter . the ber meter pro vides an estimate of the bit error rate when the recei v ed symbols are kno wn to be scrambled ones. when the lfsr is operating as a descrambler the meter counts the number of ones on the descrambler output. when the lfsr is operating as a scrambler , the ber meter counts the number of equal scrambler , and symbol detector outputs. the counter operates o v er the meter timer interv al [meter_lo w , meter_high; 0x18, 0x19]. the counter is satu- rated to 16 bits. at the end of the measurement interv al the counter is loaded into the bit error rate meter re gisters [ber_meter_lo w , ber_meter_high; 0x4c, 0x40]. the symbol histogrammer computes a coarse histogram of the recei v ed sym- bols. it operates by counting the number of ones recei v ed during meter timer interv al [meter_lo w , meter_high; 0x18, 0x19]. that is, at the start of the measure- ment interv al a counter is cleared. f or each detector output which is +1 or ?, the counter is incremented. if the detector output is +3 or ?, the count is held at its pre vious v alue. the count is saturated to 16 bits. at the end of the measurement interv al, the 8 msbs of the counter are loaded into the symbol histogram meter re gister [symbol_histogram; 0x4e]. the noise le v el meter estimates the noise at the input to the slicer . it operates by accumulating the absolute v alue of the slicer error o v er meter timer interv al [meter_lo w , meter_high; 0x18, 0x19]. at the end of the measurement interv al, the 16 msbs of the 32- bit accumulator are loaded into the noise le v el histogram meter re gister [nlm_lo w , nlm_high; 0x50, 0x51].
27 2.0 functional description 2.2 receive section bt8960 single-chip 2b1q t ransceiver n8960dsb the snr alarm pro vides a rapid indication of impulse noise disturbances and loss of signal so that correcti v e action can be tak en. the alarm is based on a sec- ond noise le v el meter . the meter is the same as the preceding noise le v el meter e xcept it operates on a dedicated snr alarm timer . the absolute v alue of the slicer error is accumulated during the timer period. at the end of the measurement interv al, the 16 msbs of the accumulator are compared ag ainst the snr alarm threshold re gister [snr_alarm_th_lo w , snr_alarm_th_high; 0x34, 0x35]. if the result is greater than this threshold, an interrupt is set in the irq_source re gister . the threshold is set via the microcomputer interf ace.
28 2.0 functional description 2.3 t iming recover y and clock interface bt8960 single-chip 2b1q t ransceiver n8960dsb 2.3 t iming recover y and clock interface the timing reco v ery and clock interf ace block diagram consists of the timing reco v ery circuit and the crystal ampli er , as detailed in figure 2-5 . the main pur - pose of this circuitry is to reco v er the clock from the recei v ed data. control elds include the hclk_freq[1,0] bits of the serial monitor source select re gister [serial_monitor_source; 0x01], the pll modes re gister [pll_modes; 0x22], the t iming reco v ery pll phase of fset re gister [pll_phase_of fsset_lo w , pll_phase_of fset_high; 0x24, 0x25] and the pll frequenc y re gister [pll_frequenc y_lo w , pll_frequenc y_high; 0x5e, 0x5f]. see the re gister section of this datasheet for descriptions of these control elds. figure 2-5. t iming recover y and clock interface block diagram hclk (35) qclk (87) xout (36) xt ali (40) xt alo (39) c10 c11 digital ground y1 timing reco v er y circuit detected symbol equaliz er error cr ystal ampli er control registers phase detector meter register [0x40, 0x41]
29 2.0 functional description 2.3 t iming recover y and clock interface bt8960 single-chip 2b1q t ransceiver n8960dsb 2.3.0.7 t iming recover y circuit the timing reco v ery circuit uses the bt8960 s internal detected symbol and equal- izer error signals to re generate the recei v ed data symbol clock (qclk). the hclk output is synchronized with the edges of the symbol clock (qclk), unlik e the xout output which is a b uf fered output of the crystal ampli er . hclk can be programmed for rates of 16, 32, or 64 times the symbol rate. the timing reco v ery circuit includes a phase detector meter that measures the a v erage v alue of the phase correction signal. this information can be used during startup to set the phase of fset in the recei v e phase select re gister [recei v e_phase_select; 0x07]. the output of the phase detector is accumulated o v er the meter timer interv al [meter_lo w , meter_high; 0x18, 0x19]. at the end of the measurement interv al, the v alue is loaded into the phase detector meter re g- ister [pdm_lo w , pdm_high; 0x40, 0x41]. the user can also bypass the timing reco v ery circuit and directly specify the frequenc y via the pll frequenc y re gister [pll_frequenc y_lo w , pll_frequenc y_high; 0x5e, 0x5f]. 2.3.0.8 cr ystal ampli er the crystal ampli er reduces the support circuitry needed for the bt8960 by elim- inating the need for an e xternal v oltage-controlled crystal oscillator (vcxo) or a crystal oscillator (xo). a crystal can be connected directly to the xt ali and xt alo pins. t able 2-6 gi v es the recommended component v alues for this cir - cuit. the crystal ampli er can also accommodate an e xternal clock input by con- necting the e xternal clock to the xt ali input pin. t able 2-6. cr ystal oscillator circuit component v alues component value y1 32 times the data rate
30 2.0 functional description 2.4 channel unit interface bt8960 single-chip 2b1q t ransceiver n8960dsb 2.4 channel unit interface the quaternary signals of the channel unit interf ace ha v e four modes which are programmable through bits 0 and 1 of the channel unit interf ace modes re gister [cu_interf ace_modes; 0x06]. the y are: serial sign-bit rst, serial magnitude-bit rst, parallel master , and parallel sla v e. in serial mode, a bit rate clock (bclk) is output at twice the symbol rate. the sign and magnitude bits of the recei v e data are output through rd a t on the rising edge of bclk. the sign and magnitude bits of the transmit data are sam- pled on the f alling edge of bclk at the td a t input. the sign bit is transferred rst, follo wed by the magnitude bit of a gi v en symbol in sign-bit rst mode, while the opposite occurs in magnitude-bit rst mode. the clock relationships for serial sign-bit rst mode are illustrated in figure 2-6 . in parallel master mode, the sign and magnitude recei v e data is output through rq[1] and rq[0], respecti v ely , on the rising edge of qclk. the quaternary transmit data is sampled on the f alling edge of qclk. this clock and data rela- tionship is illustrated in figure 2-7 . figure 2-6. serial sign-bit first mode qclk bclk rd a t td a t sign 0 magnitude 0 bit-rate cloc k sign 1 magnitude 1 sign 2 sign 0 magnitude 0 sign 1 magnitude 1 sign 2 figure 2-7. parallel master mode qclk sign 0 sign 2 sign 1 magnitude 0 magnitude 1 magnitude 2 rq[1]/tq[1] rq[0]/tq[0]
31 2.0 functional description 2.4 channel unit interface bt8960 single-chip 2b1q t ransceiver n8960dsb p arallel sla v e mode uses rbclk and tbclk inputs to synchronize data transfer . rbclk and tbclk must be frequenc y-lock ed to qclk, though the use of tw o internal fifos allo w an arbitrary phase relationship to qclk. tq[1] and tq[0] are sampled on the acti v e edge of tbclk, as programmed through the mci. rq[1] and rq[0] are output on the acti v e edge of rbclk, also as pro- grammed through the mci. the clock relationships for the case where tbclk is programmed to be f alling-edge acti v e and rbclk is rising-edge acti v e are illus- trated in figure 2-8 . figure 2-8. parallel slave mode tbclk sign 0 sign 2 sign 1 magnitude 0 magnitude 1 magnitude 2 tq[1] tq[0] rbclk sign 0 sign 2 sign 1 magnitude 0 magnitude 1 magnitude 2 rq[1] rq[0]
32 2.0 functional description 2.5 microcomputer interface bt8960 single-chip 2b1q t ransceiver n8960dsb 2.5 microcomputer interface the microcomputer interf ace pro vides operational mode control and status through internal re gisters. a microcomputer write sets the operating modes to the appropriate re gisters. a read to a re gister v eri es the operating mode or pro vides the status. the microcomputer interf ace can be programmed to generate an inter - rupt on certain conditions. 2.5.1 source code rockwell pro vides portable c-source code under a no-cost licensing agreement. this source code pro vides a startup procedure, as well as diagnostic and system monitoring functions. 2.5.2 microcomputer read/write the microcomputer interf ace uses either an 8-bit-wide multiple x ed address-data b us (intel-style), or an 8-bit-wide data b us and another separate 8-bit-wide address b us (motorola-style) for e xternal data communications. the interf ace pro vides access to the internal control and status re gisters, coef cients, and microcode ram. the interf ace is compatible with intel or motorola microcom- puters, and is con gured with the inputs, mo tel and muxed. mo tel lo w selects intel-type microcomputer and control signals: ale, cs , rd , and wr . mo tel high selects motorola-type microcomputer and control signals: ale, cs , ds , and r/ w . muxed high con gures the interf ace to use the multiple x ed address-data b us with both the address and data on the ad[7:0] pins. muxed lo w con gures the interf ace to use separate address and data b used with the data on the ad[7:0] pins and the address on the addr[7:0] pins. the read y pin is pro vided to indicate when the bt8960 is ready to transfer data and can be used by the microcomputer to insert w ait states in read or write c ycle. the microcomputer interf ace pro vides access to a 256-byte internal address space. these re gisters pro vide con guration, control, status, and monitoring capa- bilities. meter v alues are read lo wer -byte then upper -byte. when the lo wer -byte is read, the upper -byte is latched at the corresponding v alue. this ensures that multi- ple byte v alues correspond to the same reading. most information can be directly read or written; ho we v er , the lter coef cients require an indirect access.
33 2.0 functional description 2.5 microcomputer interface bt8960 single-chip 2b1q t ransceiver n8960dsb 2.5.2.1 ram access registers the internal rams of the transmit lter , lec, nec, dfe, equalizer , and micro- code are accessed indirectly . the y all share a common data re gister which is used for both read and write operations: access data re gister [access_data_byte[3:0]; [0x7c?x7f]. each ram has an indi vidual read select and write select re gister . these re gisters specify the location to access and trigger the actual ram read or write. t o perform a read, the address of the desired ram location is rst written to the corresponding read tap select re gister . t w o symbol periods afterw ards, the indi vidual bytes of that location are a v ailable for reading from the access data re gister . t o perform a write, the v alue to be written is rst stored in the access data re gister . the address of the af fected ram location is then written to the corre- sponding write tap select re gister . when writing the same v alue to multiple loca- tions, it is not necessary to re write the access data re gister . t o assure reliable access to the embedded rams, internal read and write operations are performed synchronous to the symbol clock. this has the ef fect of limiting access to these internal rams to one e v ery other c ycle. when reading or writing multiple lter coef cients, it may be desirable to freeze adaptation so that all v alues will correspond to the same state. 2.5.2.2 multiplexed address/data bus the timing for a read or write c ycle is stated e xplicitly in the electrical and mechanical speci cations section. during a read operation, an e xternal micro- computer places an address on the address-data b us which is then latched on the f alling edge of ale. data is placed on the address-data b us after cs , rd, or ds go lo w . the read c ycle is completed with the rising edge of cs , rd , or ds . a write operation latches the address from the address-data b us at the f alling edge of ale. the microcomputer places data on the address-data b us after cs, wr, or ds go lo w . motorola mci will ha v e r/ w f alling edge preceding the f all- ing edge of cs and ds . the rising edge of r/ w will occur after the rising edge of cs and ds . data is latched on the address-data b us on the rising edge of wr or ds . 2.5.2.3 separated address/ data bus the timing for a read or write c ycle using the separated address and data b uses is essentially the same as o v er the multiple x ed b us. the one e xception is that the address must be dri v en onto the addr[7:0] b us rather than the ad[7:0] b us. 2.5.3 interrupt request the twelv e interrupt sources consist of: eight timers, a f ar -end signal high alarm, a f ar -end signal lo w alarm, a snr alarm, and a scrambler synchronization detec- tion. all of the interrupts are requested on a common pin, irq . each interrupt may be indi vidually enabled or disabled through the interrupt mask re gisters [mask_lo w_re g, mask_high_re g; 0x02, 0x03]. the cause of an interrupt is deter - mined by reading the t imer source re gister [timer_source; 0x04] and the irq source re gister [irq_source; 0x05]. the timer interrupt status is set only when the timer transitions to zero. alarm interrupts cannot be cleared while the alarm is acti v e. in other w ords, it cannot be cleared while the condition still e xists. irq is an open-drain output and must be tied to a pull-up resistor . this allo ws irq to be tied together with a common interrupt request.
34 2.0 functional description 2.5 microcomputer interface bt8960 single-chip 2b1q t ransceiver n8960dsb 2.5.4 reset the reset input ( rst ) is an acti v e-lo w input that places the transcei v er in an inac- ti v e state by setting the mode bit (0) in the global modes and status re gister [global_modes; 0x00]. an internal supply monitor circuit ensures that the trans- cei v er will be in an inacti v e state upon initial application of po wer to the chip. 2.5.5 registers the bt8960 has man y directly addressable re gisters. these re gisters include con- trol and monitoring functions. write operations to unde ned re gisters will ha v e unpredictable ef fects. read operations from unde ned re gisters will ha v e unde- ned results. 2.5.6 t imers eight timers are inte grated into the bt8960 to control the v arious on-chip meters and to aid the microcomputer in stepping through the e v ents of the startup sequence. the structure of each timer includes do wn counter , zero detect logic, and con- trol circuitry , which determines when the counter is reloaded or decremented. f or each of the eight timers, there is a 2-byte timer interv al re gister that deter - mines the v alue from which the timer decrements. there are three 8-bit re gisters: the t imer restart re gister [timer_restart; 0x0c], the t imer enable re gister [timer_enable; 0x0d], and the t imer continuous mode re gister [timer_continuous; 0x0e]. these re gisters control the operation of the timers. each bit of the 8-bit re gisters corresponds to a timer . each logic-high bit in timer_restart acts as an e v ent that causes the corresponding timer to reload. each logic-high bit in timer_enable acts to enable the corresponding timer . each logic- high bit in timer_continuous acts to reload the counter after timing out. each counter is loaded with the v alue in its interv al re gister . the counter dec- rements until it reaches zero. upon reaching zero, an interrupt is generated if enabled by the interrupt mask lo w re gister [mask_lo w_re g, mask_high_re g; 0x02, 0x03]. the interrupt is edge-triggered so that only one interrupt will be caused by a single time out.
35 2.0 functional description 2.5 microcomputer interface bt8960 single-chip 2b1q t ransceiver n8960dsb a prescaler may precede the timer . this increases the time span a v ailable at the e xpense of resolution. only the startup timers ha v e prescalers. t able 2-7 pro- vides summary information on the timers. f our timers are pro vided for use in timing startup e v ents. these timers share a single prescaler which di vides the symbol clock by 1,024 and supplies this slo w clock to the four counters. the timers are: startup t imer 1, startup t imer 2, startup t imer 3, and startup t imer 4. each one is independent, with separate interv al timer v alues and interrupts. t w o timers control the measurement interv als for the v arious meters: the snr alarm t imer and the meter t imer . the snr alarm t imer is used only by the lo w snr, while the meter t imer is used by all other meters, e xcluding the lo w snr meter . their respecti v e interrupts for each timer signal are set when the y e xpire. there are no prescalers for these timers; the y count at the symbol rate. both tim- ers are normally used in the continuous mode. t w o timers are pro vided for general use: general purpose t imer 3 and gen- eral purpose t imer 4. both timers are identical. there are no prescalers for these timers; the y count at the symbol rate. each timer signals an interrupt when it e xpires. t able 2-7. t imers timer name purpose clock rate control bits startup t imer 1 startup events symbol rate ? 1024 sut 1 startup t imer 2 startup events symbol rate ? 1024 sut 2 startup t imer 3 startup events symbol rate ? 1024 sut 3 startup t imer 4 startup events symbol rate ? 1024 sut 4 snr alarm t imer snr measurement symbol rate snr meter t imer measurement symbol rate meter general purpose t imer 3 miscellaneous symbol rate t3 general purpose t imer 4 miscellaneous symbol rate t4
36 2.0 functional description 2.6 t est and diagnostic interface (jt ag) bt8960 single-chip 2b1q t ransceiver n8960dsb 2.6 t est and diagnostic interface (jt ag) as the comple xity of communications chips increases, the need to easily access indi vidual chips for pcb v eri cation is becoming vital. as a result, special cir - cuitry has been incorporated within the transcei v er which complies fully with ieee standard 1149.1-1990, ?tandard t est access port and boundary scan architecture?set by the joint t est action group. jt a g has four dedicated pins that comprise the t est access port (t ap): t est mode select (tms), t est clock (tck), t est data input (tdi), and t est data out (tdo). v eri cation of the inte grated circuit and its connection to other modules on the printed circuit board can be achie v ed through these four t ap pins. jt a g s approach to testability utilizes boundary scan cells placed at each dig- ital pin, both inputs and outputs. all scan cells are interconnected into a bound- ary-scan re gister which applies or captures test data used for functional v eri cation of the pc board interconnection. jt a g is particularly useful for board testers using functional testing methods. w ith boundary-scan cells at each digital pin, the ability to apply and capture the respecti v e logic le v els is pro vided. since all of the digital pins are intercon- nected as a long shift re gister , the t ap logic has access and control of all neces- sary pins to v erify functionality . f or mix ed signal ics, the chip boundary de nition is e xpanded to include the on-chip interf ace between digital and analog circuitry . internal supply monitor circuitry ensures that each pin is initialized to operate as an 2b1q transcei v er , instead of jt a g test mode during a po wer -up sequence. the jt a g standard de nes an optional de vice identi cation re gister . this re g- ister is included and contains a re vision number , a part number , and a manuf actur - ers identi cation code speci c to rockwell. access to this re gister is through the t ap controller via the standard jt a g instruction set (see t able 2-8 ). a v ariety of v eri cation procedures can be performed through the t ap con- troller . board connecti vity can be v eri ed at all digital pins through a set of four instructions accessible through the use of a state machine standard to all jt a g controllers. refer to the ieee 1149.1 speci cation for details concerning the instruction re gister and jt a g state machine. a boundry scan description lan- guage (bsdl) le for the bt8960 is also a v ailable from the f actory upon request. t able 2-8. jt ag device identi cation register version (1) part number manufacturer id 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 0x0 0x2300 0x0d6 4 bits 16 bits 11 bits notes: (1). consult factory for current version number. tdo
37 n8960dsb 3.0 registers 3.1 conventions unless otherwise noted, the follo wing con v entions apply to all applicable re gister descriptions: f or storage of multiple-bit data elds within a single byte-wide re gister , the least signi cant bits (lsbs) of the eld are located at the lo wer re gister -bit positions, while the most signi cant bits (msbs) are located at the higher positions. if only a single data eld is stored in a byte-wide re gister , the eld will be justi ed such that the lsb of the eld is located in the lo west re gister -bit position, bit 0. f or storage of multiple-byte data w ords across multiple byte-wide re gisters, the least signi cant bytes of the w ord are located at the lo wer byte-address locations, while the most signi cant bytes are located at the higher byte-address locations. when writing to an y control or data re gister with less than all 8-bit positions de ned, a logic zero v alue must be assigned to each unused/unde ned/reserv ed position. writing a logic one v alue to an y of these positions may cause unde ned beha vior . when reading from an y control/status or data re gister with less than all 8-bit positions de ned, an inde- terminate v alue will be returned from each unused/unde ned/reserv ed position. re gister v alues are not af fected by rst pin assertion, e xcept for the mode bit of the global modes and status re gister [global_modes; 0x00], the hclk_freq[1,0] eld of the serial monitor source select re g- ister [serial_monitor_source; 0x01] and the clk_freq[1,0] eld of the pll modes re gister [pll_modes; 0x22]. upon rst pin assertion, all ram is lost e xcept for the equalizer microcode and scratch pad ram. the initial v alues of all re gisters and ram are unde ned after po wer is applied. exceptions include the mode bit of the global modes and status re gister , the hclk_freq[1,0] eld of the serial monitor source select re gister and the clk_freq[1,0] eld of the pll modes re gister . in addition, the jt a g state is reset when po wer is applied. the re gister and bit mnemonics used here are based on the mnemonics used in the rockwell bit pump softw are.
registers register summar y bt8960 single-chip 2b1q t ransceiver 38 n8960dsb 3.2 register summar y t able 3-1. register t able (1 of 6) addr (hex) register label read write bit number 7 6 5 4 3 2 1 0 0x00 global_modes r/w hw_revision[ 3] hw_revision[2] hw_revision[1] hw_revision[0] part_id[2] part_id[1] part_id[0] mode 0x01 serial_monitor_sour ce r/w hclk_freq[1] hclk_freq[0] smon[5] smon[4] smon[3] smon[2] smon[1] smon[0] 0x02 mask_low_reg r/w t4 t3 snr meter sut4 sut3 sut2 sut1 0x03 mask_high_reg r/w sync high_felm low_felm low_snr 0x04 timer_sour ce r/w t4 t3 snr meter sut4 sut3 sut2 sut1 0x05 irq_sour ce r/w sync high_felm low_felm low_snr 0x06 cu_inter face_modes r/w tbclk_pol rbclk_pol fos_mode inter face_ mode1 inter face_ mode[0] 0x07 receive_phase_select r/w rphs[3] rphs[2] rphs[1] rphs[0] 0x08 linear_ec_modes r/w enable_dc_tap adapt_coef cien ts zero_coef cients zero_output adapt_gain[1] adapt_gain[0] 0x09 nonlinear_ec_modes r/w negate_symb ol symbol_ delay[2] symbol_ delay[1] symbol_delay[0] adapt_ coef cients zero_ coef cients zero_output adapt_gain 0x0a dfe_modes r/w adapt_ coef cients zero_ coef cients zero_output adapt_gain 0x0b transmitter_modes r/w isolated_ pulse[1] isolated_ pulse[0] transmitter_off htur_lfsr data_sour ce[2] data_sour ce[1] data_sour ce[0] 0x0c timer_restart r/w t4 t3 snr meter sut4 sut3 sut2 sut1 0x0d timer_enable r/w t4 t3 snr meter sut4 sut3 sut2 sut1 0x0e timer_continuous r/w t4 t3 snr meter sut4 sut3 sut2 sut1
registers register summar y bt8960 single-chip 2b1q t ransceiver 39 n8960dsb 0x0f reser ved2 r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x10 sut1_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x11 sut1_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x12 sut2_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x13 sut2_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x14 sut3_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x15 sut3_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x16 sut4_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x17 sut4_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x18 meter_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x19 meter_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x20 reser ved9 r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x1a snr_timer_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x1b snr_timer_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x1c t3_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x1d t3_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x1e t4_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x1f t4_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x21 adc_control r/w loop_back[1] loop_back[0] gain[2] gain[1] gain[0] 0x22 pll_modes r/w clk_freq[1] clk_freq[0] phase_detector_ gain[1] phase_detector_ gain[0] freeze_pll pll_gain[1] pll_gain[0] t able 3-1. register t able (2 of 6) addr (hex) register label read write bit number 7 6 5 4 3 2 1 0
registers register summar y bt8960 single-chip 2b1q t ransceiver 40 n8960dsb 0x23 reser ved10 r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x24 pll_phase_offset_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x25 pll_phase_offset_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x26 dc_offset_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x27 dc_offset_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x28 tx_calibrate r/w tx_calibrate[3] tx_calibrate[2] tx_calibrate[1] tx_calibrate[0] 0x29 tx_gain r/w tx_gain[3] tx_gain[2] tx_gain[1] tx_gain[0] 0x2a noise_histogram_th_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x2b noise_histogram_th_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x2c ep_pause_th_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x2d ep_pause_th_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x2e scr_sync_th r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x30 far_end_high_alarm_th_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x31 far_end_high_alarm_th_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x32 far_end_low_alarm_th_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x33 far_end_low_alarm_th_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x34 snr_alarm_th_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x35 snr_alarm_th_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x36 cursor_level_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x37 cursor_level_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] t able 3-1. register t able (3 of 6) addr (hex) register label read write bit number 7 6 5 4 3 2 1 0
registers register summar y bt8960 single-chip 2b1q t ransceiver 41 n8960dsb 0x38 dagc_target_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x39 dagc_target_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x3a detector_modes r/w enable_peak_ detector output_mux_ control[1] output_mux_ control[0] scr_out_to_dfe two_level lfsr_lock htur_lfsr descr_on 0x3b peak_detector_delay r/w d[3] d[2] d[1] d[0] 0x3c dagc_modes r/w eq_error_ adaption adapt_ coef cient adapt_gain 0x3d ffe_modes r/w adapt_last_coeff zero_ coef cients adapt_ coef cient adapt_gain 0x3e ep_modes r/w zero_output zero_ coef cients adapt_ coef cients adapt_gain 0x40 pdm_low r/w d[17] d[16] d[15] d[14] d[13] d[12] d[11] d[10] 0x41 pdm_high r/w d[25] d[24] d[23] d[22] d[21] d[20] d[19] d[18] 0x42 over ow_meter r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x44 dc_meter_low r/w d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] 0x45 dc_meter_high r/w d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 0x46 slm_low r/w d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] 0x47 slm_high r/w d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 0x48 felm_low r/w d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] 0x49 felm_high r/w d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 0x4a noise_histogram_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x4b noise_histogram_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] t able 3-1. register t able (4 of 6) addr (hex) register label read write bit number 7 6 5 4 3 2 1 0
registers register summar y bt8960 single-chip 2b1q t ransceiver 42 n8960dsb 0x4c ber_meter_low r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x4d ber_meter_high r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x4e symbol_histogram r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x50 nlm_low r/w d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] 0x51 nlm_high r/w d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 0x5e pll_frequency_low r/w d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[15] 0x5f pll_frequency_high r/w d[30] d[29] d[28] d[27] d[26] d[25] d[24] d[23] 0x70 linear_ec_tap_select_read r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x71 linear_ec_tap_select_write r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x72 nonlinear_ec_tap_select_read r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x73 nonlinear_ec_tap_select_write r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x74 dfe_tap_select_read r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x75 dfe_tap_select_write r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x76 sp_tap_select_read r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x77 sp_tap_select_write r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x78 eq_add_read r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x79 eq_add_write r/w d[5] d[4] d[3] d[2] d[1] d[0] t able 3-1. register t able (5 of 6) addr (hex) register label read write bit number 7 6 5 4 3 2 1 0
registers register summar y bt8960 single-chip 2b1q t ransceiver 43 n8960dsb 0x7a eq_microcode_add_read r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x7b eq_microcode_add_write r/w d[5] d[4] d[3] d[2] d[1] d[0] 0x7c access_data_byte0 r/w d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0x7d access_data_byte1 r/w d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 0x7e access_data_byte2 r/w d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] 0x7f access_data_byte3 r/w d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] t able 3-1. register t able (6 of 6) addr (hex) register label read write bit number 7 6 5 4 3 2 1 0
44 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.1 0x00?lobal modes and status register (global_modes) hw_revision[3:0] chip re vision number?ead-only unsigned binary eld encoded with the chip re vision number . smaller v alues represent earlier v ersions while lar ger v alues represent later v ersions. the zero v alue represents the original prototype release. consult f actory for current v alue and re vision. part _id[2:0] p art id?ead-only binary eld set to binary 001 identifying the part as bt8960. mode po wer do wn mode?ead/write control bit. when set, stops all lter processing and zeros the transmit output for reduced po wer consumption. all ram contents are preserv ed. the mode bit is automatically set by rst assertion and upon initial po wer application. it can be cleared only by writing a logic zero, at which time lter processing and transmitter operation can pro- ceed. 3.2.2 0x01?erial monitor source select register (serial_monitor_source) hclk_freq[1,0] hclk frequenc y select?ead/write binary eld selects the frequenc y of the hclk output. 7 6 5 4 3 2 1 0 hw_revision[3] hw_revision[2] hw_revision[1] hw_revision[0] part_id[2] part_id[1] part_id[0] mode 7 6 5 4 3 2 1 0 hclk_freq[1] hclk_freq[0] smon[5] smon[4] smon[3] smon[2] smon[1] smon[0] hclk_freq[1] hclk_freq[0] hclk frequency 0 0 symbol frequency (f qclk ) times 64 hclk_freq[1,0] is set to ?0?upon assertion of the rst pin and power -on detection. 0 1 symbol frequency (f qclk ) times 16 1 0 symbol frequency (f qclk ) times 32 1 1 symbol frequency (f qclk ) times 64
45 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb smon[5:0] serial monitor source select?ead/write binary eld selects the serial monitor (smon) out- put source. 3.2.3 0x02?nterrupt mask register low (mask_low_reg) independent read/write mask bits for each of the t imer source re gister [timer_source; 0x04] interrupt ags. a logic one represents the mask ed condition. a logic zero represents the unmask ed condition. all mask bits beha v e identically with respect to their corresponding interrupt ags. setting a mask bit pre v ents the corre- sponding interrupt ag from af fecting the irq output. clearing a mask allo ws the interrupt ag to af fect irq output. unmasking an acti v e interrupt ag will immediately cause the irq output to go acti v e, if currently inac- ti v e. masking an acti v e interrupt ag will cause irq to go inacti v e, if no other unmask ed interrupt ags are set. t4 general purpose t imer 4 t3 general purpose t imer 3 snr snr alarm t imer meter meter t imer sut4 startup t imer 4 sut3 startup t imer 3 sut2 startup t imer 2 sut1 startup t imer 1 smon[5:0] source decimal binary 0 ?47 00 0000 ?10 1111 equalizer register file 48 11 0000 digital front-end output/lec input 49 11 0001 linear echo replica 50 11 0010 dfe subtactor output/ep input 51 11 0011 ep subtractor output/slicer input 52 11 0100 t iming recover y phase detector output/loop filter input 53 11 0101 t iming recover y loop filter output/frequency synthesizer input 7 6 5 4 3 2 1 0 t4 t3 snr meter su4 sut3 sut2 sut1
46 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.4 0x03?nterrupt mask register high (mask_high_reg) independent read/write mask bits for each of the irq source re gister [irq_source; 0x05] interrupt ags. indi- vidual mask bit beha vior is identical to that speci ed for interrupt mask re gister lo w [mask_lo w_re g; 0x02]. sync sync indication high_felm f ar -end le v el meter high alarm low_felm f ar -end le v el meter high alarm low_snr signal-to-noise ratio lo w alarm 3.2.5 0x04? imer source register (timer_source) independent read/write (zero only) interrupt ags, one for each of eight internal timers. each ag bit is set and stays set when its corresponding timer v alue transitions from one to zero. if unmask ed, this e v ent will cause the irq output to be acti v ated. flags are cleared by writing them with a logic zero v alue. once cleared, a steady- state timer v alue of zero will not cause a ag to be reasserted. clearing an unmask ed ag will cause the irq output to return to the inacti v e state, if no other unmask ed interrupt ags are set. t4 general purpose t imer 4 t3 general purpose t imer 3 snr snr alarm t imer meter meter t imer sut4 startup t imer 4 sut3 startup t imer 3 sut2 startup t imer 2 sut1 startup t imer 1 7 6 5 4 3 2 1 0 sync high_felm low_felm low_snr 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1
47 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.6 0x05?rq source register (irq_source) independent read/write (zero only) interrupt ags, one for each of four internal sources. each ag bit is set and stays set when its corresponding source indicates that a v alid interrupt condition e xists. if unmask ed, this e v ent will cause the irq output to be acti v ated. writing a logic zero to an interrupt ag whose underlying condition no longer e xists will cause the ag to be immediately cleared. attempting to clear a ag whose underlying con- dition still e xists will not immediately clear the ag, b ut will allo w it to remain set until the underlying condition e xpires, at which time the ag will be cleared automatically . the clearing of an unmask ed ag will cause the irq output to return to an inacti v e state, if no other unmask ed interrupt ags are set. sync sync indication?cti v e when the sync detector is enabled and its accumulated equi v alent comparisons e xceeds (greater than) the threshold v alue stored in the scrambler sync thresh- old re gister [scr_sync_th; 0x2e]. high_felm f ar -end le v el meter high alarm?cti v e when the f ar -end le v el meter v alue e xceeds (greater than) the threshold stored in the f ar -end high alarm threshold re gisters [f ar_end_high_alarm_th_lo w , f ar_end_high_alarm_th_high; 0x30?x31]. low_felm f ar -end le v el meter lo w alarm?cti v e when the f ar -end le v el meter v alue e xceeds (less than) the threshold stored in the f ar -end lo w alarm threshold re gisters [f ar_end_lo w_alarm_th_lo w , f ar_end_lo w_alarm_th_high; 0x32?x33]. low_snr signal-to-noise ratio lo w alarm?cti v e when the snr alarm meter v alue e xceeds (greater than) the threshold stored in the snr alarm threshold re gisters [snr_alarm_th_lo w , snr_alarm_th_high; 0x34?x35]. 3.2.7 0x06?hannel unit interface modes register (cu_interface_modes) tbclk_pol t ransmit baud clock polarity?ead/write control bit de nes the polarity of the tbclk input while in the parallel sla v e interf ace mode. when set, tq[1,0] is sampled on the f alling edge of tbclk; when cleared, tq[1,0] is sampled on the rising edge. rbclk_pol recei v e baud clock polarity?ead/write control bit de nes the polarity of the rbclk input while in the parallel sla v e interf ace mode. when set, rq[1,0] is updated on the f alling edge of rbclk; when cleared, rq[1,0] is updated on the rising edge. fos_mode fifo s mode?ead/write control bit used to stagger the transmit and recei v e fifo s read and write pointers while in the parallel sla v e interf ace mode. a logic one forces the pointers to a staggered position, while a logic zero allo ws them to operate normally . must be rst set, then cleared once after qclk-tbclk-rbclk frequenc y lock is achie v ed to maximize phase- error tolerance. interface_ mode[1,0] interf ace mode?ead/write binary eld speci es one of four operating modes for the channel unit interf ace. 7 6 5 4 3 2 1 0 sync high_felm low_felm low_snr 7 6 5 4 3 2 1 0 tbclk_pol rbclk_pol fos_mode inter face_mode[1] inter face_mode[0]
48 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.8 0x07?eceive phase select register (receive_phase_select) rphs[3:0] recei v e phase select?ead/write binary eld that de nes the relati v e phase relationship between qclk and the sampling point of the adc. the rising edges of qclk corresponds to the adc sampling point when rphs = 0000. each binary increment of rphs represents a one- sixteenth qclk period delay in the sampling point relati v e to qclk. 3.2.9 0x08?inear echo canceller modes register (linear_ec_modes) enable_dc_tap enable dc t ap?ead/write control bit which, when set, forces a constant +1 v alue into the last data tap of the linear echo canceller (lec). this condition enables cancellation of an y residual dc of fset present at the input to the lec. when cleared, the last data tap operates nor - mally , as the oldest transmit data sample. adapt_coef cents adapt coef cients?ead/write control bit which enables coef cient adaptation when set; dis- ables/freezes adaptation when cleared. coef cient v alues are preserv ed when adaptation is dis- abled. zero_coef cients zero coef cients?ead/write control bit that continuously zeros all coef cients when set; allo ws normal coef cient updates, if enabled, when cleared. this beha vior dif fers slightly from the similar function (zero_coef cients) of the ffe and ep lters. interface mode [1:0] mode pin functions 91 90 88 89 85 86 00 parallel master ?arallel quat transfer synchronized to qclk out. not used not used rq[1] rq[0] tq[1] tq[0] 01 parallel slave?arallel quat transfer synchronized to separate tbclk and rbclk inputs. tbclk rbclk rq[1] rq[0] tq[1] tq[0] 10 serial, magnitude first. serial quat transfer synchronized to bclk out; magnitude-bit rst followed by sign bit. not used not used rda t bclk tda t not used 11 serial, sign first. serial quat transfer synchronized to bclk out; sign-bit rst followed by magnitude bit. not used not used rda t bclk tda t not used 7 6 5 4 3 2 1 0 rphs[3] rphs[2] rphs[1] rphs[0] 7 6 5 4 3 2 1 0 enable_dc_tap adapt_ coef cients zero_coef cients zero_output adapt_gain[1] adapt_gain[0]
49 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb zero_output zero output?ead/write control bit which, when set, zeros the echo replica before subtrac- tion from the input signal. achie v es the af fect of disabling or bypassing the echo cancellation function. does not disable coef cient adaptation. when cleared, normal echo canceller opera- tion is performed. adapt_gain[1,0] adaptation gain?ead/write binary eld which speci es the adaptation g ain. 3.2.10 0x09?onlinear echo canceller modes register (nonlinear_ec_modes) negate_symbol ne g ate symbol?ead/write control bit which, when set, in v erts (2 s complement) the recei v e signal path at the output of the nonlinear echo canceller . when cleared, the signal path is unaf- fected. this function is independent of all other nec mode settings. symbol_delay[2:0] symbol delay?ead/write binary eld which speci es the number of symbol delays inserted in the transmit symbol input path. adapt_coef cients adapt coef cients?ame function as lec modes re gister [linear_ec_modes; 0x08]. zero_coef cients zero coef cients?ame function as lec modes re gister . zero_output zero output?ame function as lec modes re gister . adapt_gain adaptation gain?ead/write control bit which speci es the adaptation g ain. when set, the adaptation g ain is eight times higher than when cleared. adapt_gain[1,0] normalized gain 00 1 01 4 10 64 11 512 7 6 5 4 3 2 1 0 negate_symbol symbol_delay[2] symbol_delay[1] symbol_delay[0] adapt_ coef cients zero_coef cients zero_output adapt_gain
50 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.11 0x0a?ecision feedback equalizer modes register (dfe_modes) adapt_coef cents adapt coef cients?ead/write control bit which enables coef cient adaptation when set; dis- ables/freezes adaptation when cleared. coef cient v alues are preserv ed when adaptation is dis- abled. zero_coef cients zero coef cients?ead/write control bit which continuously zeros all coef cients when set; allo ws normal coef cient updates, if enabled, when cleared. zero_output zero output?ead/write control bit which, when set, zeros the equalizer correction signal before subtraction from the input signal. achie v es the af fect of disabling or bypassing the equalization function. does not disable coef cient adaptation. when cleared, normal equalizer operation is performed. adapt_gain adaptation gain?ead/write control bit which speci es the adaptation g ain. when set, the adaptation g ain is eight times higher than when cleared. 3.2.12 0x0b? ransmitter modes register (transmitter_modes) isolated_pulse[1,0] isolated pulse le v el select?ead/write binary eld that selects one of four output pulse le v- els while in the isolated pulse transmitter mode. transmitter_off t ransmitter of f?ead/write control bit that zeros the output of the transmitter when set; allo ws normal transmitter operation (as de ned by data_source[2:0]) when cleared. htur_lfsr remote unit (htu-r/ntu) polynomial select?ead/write control bit selects one of tw o feedback polynomials for the transmit scrambler . when set, this bit selects the remote unit transmit polynomial (x ?3 + x ?8 + 1); when cleared, it selects the local unit (htu-c/l tu) polynomial (x ?3 + x ? + 1). data_source[2:0] data source?ead/write binary eld that selects the data source and mode of the transmitter output. the transmitter must be enabled (transmitter_of f = 0) for these modes to be acti v e. 7 6 5 4 3 2 1 0 adapt_ coef cients zero_coef cients zero_output adapt_gain 7 6 5 4 3 2 1 0 isolated_pulse[1] isolated_pulse[0] transmitter_off htur_lfsr data_sour ce[2] data_sour ce[1] data_sour ce[0] isolated_pulse[1,0] output pulse level 00 ? 01 ? 10 +3 11 +1
51 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb data_source [2:0] transmitter mode 000 isolated pulse. level selected by isolated_pulse[1:0]. the meter timer must be enabled and in the continuous mode. the pulse repetition inter val is determined by the meter timer countdown inter val. 001 four -level scrambled detector loopback. sign and magnitude bits from the receiver detector are scrambled and looped back to the transmitter . feedback polynomial deter - mined by the htur_lfsr control bit. 010 four -level unscrambled data. t ransmits the four -level (2b1q) sign and magnitude bits from the channel unit transmit inter face without scrambling. 011 four -level scrambled ones. t ransmits a scrambled, constant high logic level as a four - level (2b1q) signal. feedback polynomial determined by the htur_lfsr control bit. 100 reser ved. 101 four -level scrambled data. scrambles and transmits the four -level (2b1q) sign and mag- nitude bits from the channel unit transmit inter face. feedback polynomial determined by the htur_lfsr control bit. 110 t wo-level unscrambled data. constantly for ces the magnitude bit from the channel unit transmit inter face to a logic zero and transmits the resulting two-level signal (as deter - mined by the sign bit) without scrambling. v alid output levels limited to +3, ?. 111 t wo-level scrambled ones. t ransmits a scrambled, constant high-logic level as a two- level signal. feedback polynomial determined by the htur_lfsr control bit. scrambler is run at the symbol rate (half-bit rate) to produce the sign bit of the transmitted signal while the magnitude bit is sour ced with a constant logic zero. v alid output levels limited to +3, ?.
52 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.13 0x0c? imer restart register (timer_restart) independent read/write restart bits, one for each of the eight internal timers. setting an indi vidual bit causes the associated timer to be reloaded with the contents of its interv al re gister . f or the four symbol-rate timers (meter , snr , t3, t4), reloading will occur within one symbol period. f or the four startup timers (sut1?), reloading will occur within 1,024 symbol periods. once reloaded, the restart bit is automatically cleared. if a restart bit is set and then cleared (by writing a logic zero) before the reload actually tak es place, no timer reload will occur . once reloaded, if enabled in the t imer enable re gister [timer_enable; 0x0d], the timer will be gin counting do wn to w ard zero; otherwise, it will hold at the interv al re gister v alue. t4 general purpose t imer 4 t3 general purpose t imer 3 snr snr alarm t imer meter meter t imer sut4 startup t imer 4 sut3 startup t imer 3 sut2 startup t imer 2 sut1 startup t imer 1 3.2.14 0x0d? imer enable register (timer_enable) independent read/write enable bits, one for each of the eight internal timers. when an y indi vidual bit is set, the corresponding timer is enabled for counting do wn from its current v alue to w ard zero. f or the four symbol-rate timers (meter , snr , t3, t4), counting will be gin within one symbol period. f or the four startup timers (sut1-4), counting will be gin within 1,024 symbol periods. when an enable bit is cleared, the timer is disabled from counting while it holds its current v alue. if an enable bit is set and then cleared before a count actually tak es place, no timer countdo wn will occur . t4 general purpose t imer 4 t3 general purpose t imer 3 snr snr alarm t imer meter meter t imer sut4 startup t imer 4 sut3 startup t imer 3 sut2 startup t imer 2 sut1 startup t imer 1 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1
53 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.15 0x0e? imer continuous mode register (timer_continuous) independent read/write mode bits, one for each of the eight internal timers. when an y indi vidual bit is set, the corresponding timer is placed in the continuous count mode. while in this mode, after reaching the zero count, an enabled timer will reload the contents of its interv al re gister and continue counting. when a mode bit is cleared, the timer is tak en out of the continuous mode. while in this con guration, after reaching the zero count, an enabled timer will simply stop counting and remain at zero. 3.2.16 0x0f? est register (reser ved2) a 1-byte read/write re gister used for de vice testing by rockwell. this re gister is automatically initialized to 0x00 upon rst assertion and initial po wer application. this re gister must be initialized according to the de vice dri v er pro vided by rockwell. 3.2.17 0x10, 0x11?tartup t imer 1 inter val register (sut1_low , sut1_high) a 2-byte read/write re gister stores the countdo wn interv al for startup t imer 1 in unsigned binary format. each increment represents 1,024 symbol periods. the contents of this re gister are automatically loaded into its associ- ated timer after the timer s timer_restart bit is set, or after it counts do wn to zero while in the continuous mode. 3.2.18 0x12, 0x13?tartup t imer 2 inter val register (sut2_low , sut2_high) a 2-byte read/write re gister stores the countdo wn interv al for startup t imer 2 in unsigned binary format. each increment represents 1,024 symbol periods. the contents of this re gister are automatically loaded into its associ- ated timer after the timer s timer_restart bit is set, or after it counts do wn to zero while in the continuous mode. 3.2.19 0x14, 0x15?tartup t imer 3 inter val register (sut3_low , sut3_high) a 2-byte read/write re gister stores the countdo wn interv al for startup t imer 3 in unsigned binary format. each increment represents 1,024 symbol periods. the contents of this re gister are automatically loaded into its associ- ated timer after the timer s timer_restart bit is set, or after it counts do wn to zero while in the continuous mode. 3.2.20 0x16, 0x17?tartup t imer 4 inter val register (sut4_low , sut4_high) a 2-byte read/write re gister stores the countdo wn interv al for startup t imer 4 in unsigned binary format. each increment represents 1,024 symbol periods. the contents of this re gister are automatically loaded into its associ- ated timer after the timer s timer_restart bit is set, or after it counts do wn to zero while in the continuous mode. 3.2.21 0x18, 0x19?eter t imer inter val register (meter_low , meter_high) a 2-byte read/write re gister stores the countdo wn interv al for the meter t imer in unsigned binary format. each increment represents one symbol period. the contents of this re gister are automatically loaded into its associ- ated timer after the timer s timer_restart bit is set, or after it counts do wn to zero while in the continuous mode. 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1
54 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.22 0x20? est register (reser ved9) a 1-byte read/write re gister used for de vice testing by rockwell. this re gister is automatically initialized to 0x00 upon rst assertion and initial po wer application. this re gister must be initialized according to the de vice dri v er pro vided by rockwell. 3.2.23 0x1a, 0x1b?nr alarm t imer inter val register (snr_timer_low , snr_timer_high) a 2-byte read/write re gister stores the countdo wn interv al for the snr alarm t imer in unsigned binary format. each increment represents one symbol period. the contents of this re gister are automatically loaded into its associated timer after the timer s timer_restart bit is set, or after it counts do wn to zero while in the continuous mode. 3.2.24 0x1c, 0x1d?eneral purpose t imer 3 inter val register (t3_low , t3_high) a 2-byte read/write re gister stores the countdo wn interv al for general purpose t imer 3 in unsigned binary for - mat. each increment represents one symbol period. the contents of this re gister are automatically loaded into its associated timer after the timer s timer_restart bit is set, or after it counts do wn to zero while in the continu- ous mode. 3.2.25 0x1e, 0x1f?eneral purpose t imer 4 inter val register (t4_low , t4_high) a 2-byte read/write re gister stores the countdo wn interv al for general purpose t imer 4 in unsigned binary for - mat. each increment represents one symbol period. the contents of this re gister are automatically loaded into its associated timer after the timer s timer_restart bit is set, or after it counts do wn to zero while in the continu- ous mode.
55 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.26 0x21?dc control register (adc_control) loop_back[1,0] loopback control?ead/write binary eld specifying if loopback is enabled, and the type of loopback that is enabled. during transmitting loopback, the differential receiver inputs (rxp, rxn) are disabled. the loopback path is intended to go from the transmitter outputs (txp, txn), through the external hybrid circuit, back into the differential receiver balance inputs (rxbp, rxbn). during silent loop back, the transmitter is turned off, and the output of the pulse-shaping filter in the transmit section is internally connected to the input of the adc in the receive section. gain[2:0] gain control?ead/write binary eld speci es the g ain of the v ga. 7 6 5 4 3 2 1 0 loop_back[1] loop_back[0] gain[2] gain[1] gain[0] loop_back[1,0] function 00 normal operation (loop back disabled) 01 hybrid inputs disabled (rxbp , rxbn) 10 t ransmitting loopback 11 silent loop back gain[2:0] vga gain 000 0db 001 3 db 010 6 db 011 9 db 100 12 db 101 15 db 110 15 db 111 15 db
56 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.27 0x22?ll modes register (pll_modes) clk_freq[1,0] clock frequenc y select?ead/write binary eld speci es one of four data rate ranges for bt8960 operation. the 00 state is automatically selected by rst assertion and upon initial po wer application. the crystal or e xternal clock frequenc y must be equal to 32 times the data rate. phase_detector_ gain[1,0] phase detector gain?ead/write binary eld speci es one of four g ain settings for the tim- ing-reco v ery phase detector function. freeze_pll freeze pll?ead/write control bit. when set, this bit zeros the proportional term of the loop compensation lter and disables accumulator updates causing the pll to hold its current fre- quenc y . when cleared, proportional term ef fects and accumulator updates are enabled allo wing the pll to track the phase of the incoming data. pll_gain[1,0] pll gain?ead/write binary eld speci es the g ain (proportional and inte gral coef cients) of the loop compensation lter . 7 6 5 4 3 2 1 0 clk_freq[1] clk_freq[0] negate_symbol phase_detector_ gain[1] phase_detector_ gain[0] freeze_pll pll_gain[1] pll_gain[0] clk_freq[1,0] range data rate 00 221 to 252kbps 01 above 352 kbps 10 160 to 221 kbps 11 reser ved phase_detector_gain[1,0] normalized gain 00 1 01 2 10 4 11 reser ved pll_gain[1:0] normalized proportional coefficients normalized integral coefficients 00 1 1 01 4 32 10 16 256 11 64 4096
57 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.28 0x23? est register (reser ved10) a 3-byte read/write re gister used for de vice testing by rockwell. this re gister is automatically initialized to 0x000000 upon rst assertion and initial po wer application. this re gister must be initialized according to the de vice dri v er pro vided by rockwell. 3.2.29 0x24, 0x25? iming recover y pll phase offset register (pll_phase_offset_low , pll_phase_offset_high) a 2-byte read/write re gister interpreted as a 16-bit, 2 s-complement number . the v alue of this re gister is sub- tracted from the output of the timing-reco v ery phase detector after the phase-detector meter b ut before the loop compensation lter . 3.2.30 0x26, 0x27?eceiver dc offset register (dc_offset_low , dc_offset_high) a 2-byte read/write re gister interpreted as a 16-bit, 2 s-complement number . the v alue of this re gister is sub- tracted from the recei v er signal path at the output of the digital front end s format con v ersion block, ahead of the dc le v el and signal le v el meters. 3.2.31 0x28? ransmitter calibration register (tx_calibrate) tx_calibrate[3:0] t ransmit calibrate?-bit, 2 s-complement, read-only eld containing the nominal setting for the transmitter g ain. the v alue of the t ransmit calibration re gister is set during manuf actur - ing testing by rockwell and corresponds to the v alue required to operate the bt8960 at a nom- inal 13.5 dbm transmit po wer , assuming the recommended transformer coupling/h ybrid circuit is used. users may o v erride this calibration by writing their o wn v alue into the t ransmitter gain re gister [tx_g ain; 0x29]. 7 6 5 4 3 2 1 0 tx_calibrate[3] tx_calibrate[2] tx_calibrate[1] tx_calibrate[0]
58 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.32 0x29? ransmitter gain register (tx_gain) tx_gain[3:0] t ransmit gain? 4-bit, 2 s-complement, read/write eld controlling the transmitter g ain. upon initialization, the v alue in the t ransmitter calibration re gister [tx_calibrate; 0x28] may be written into this re gister by softw are to set the transmitter g ain to the nominal v alue, or the user may set it to another desired v alue. 7 6 5 4 3 2 1 0 tx_gain[3] tx_gain[2] tx_gain[1] tx_gain[0] tx_gain[3:0] relative transmitter gain (db) 1000 ?.60 1001 ?.36 1010 ?.13 1011 ?.91 1100 ?.69 1101 ?.48 1110 ?.27 1111 ?.07 0000 0.13 0001 0.32 0010 0.51 0011 0.70 0100 0.88 0101 1.05 0110 1.23 0111 1.40
59 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.33 0x2a, 0x2b?oise-level histogram threshold register (noise_histogram_th_low , noise_histogram_th_high) t w o-byte read/write re gister interpreted as a 16-bit, 2 s-complement number . the range of meaningful v alues is limited to positi v e inte gers between 0x0000 and 0x7fff . the v alue of this re gister is compared to the absolute v alue of the slicer error signal produced by the detector . a count of error samples that e xceed this threshold (greater than) is accumulated in the noise-le v el histogram meter . 3.2.34 0x2c, 0x2d?rror predictor pause threshold register (ep_pause_th_low , ep_pause_th_high) t w o-byte read/write re gister interpreted as a 16-bit, 2 s-complement number . the range of meaningful v alues is limited to positi v e inte gers between 0x0000 and 0x7fff . the v alue of this re gister is compared to the absolute v alue of the slicer error signal produced by the detector . the result of this comparison (slicer error greater than this threshold) is used to initiate a pause condition by zeroing the output of the error predictor correction signal before subtraction from the recei v e signal path. error predictor coef cient updates are not af fected. the pause condition lasts for a x ed 5-symbol period from the time the threshold w as last e xceeded. 3.2.35 0x2e?crambler synchronization threshold register (scr_sync_th) a 7-bit read/write re gister representing an unsigned binary number . the contents of this re gister are used to test for scrambler synchronization during the automatic-scrambler synchronization mode of the symbol detector . the test passes when the count of equi v alent scrambler and detector output bits e xceeds (greater than) the v alue of this re gister . when the auto-scrambler sync mode is not enabled, the contents of this re gister are not used. 3.2.36 0x30, 0x31?ar -end high alarm threshold register (far_end_high_alarm_th_low , far_end_high_alarm_th_high) a 2-byte read/write re gister interpreted as a 16-bit, 2 s-complement number . the range of meaningful v alues is limited to positi v e inte gers between 0x0000 and 0x7fff . the v alue of this re gister is compared to the v alue of the f ar -end le v el meter . if the meter reading e xceeds (greater than) this threshold, the high_felm interrupt ag is set in the irq source re gister [irq_source; 0x05]. 3.2.37 0x32, 0x33?ar -end low alarm threshold register (far_end_low_alarm_th_low , far_end_low_alarm_th_high) a 2-byte read/write re gister interpreted as a 16-bit, 2 s-complement number . the range of meaningful v alues is limited to positi v e inte gers between 0x0000 and 0x7fff . the v alue of this re gister is compared to the v alue of the f ar -end le v el meter . if the meter reading e xceeds (less than) this threshold, the lo w_felm interrupt ag is set in the irq source re gister [irq_source; 0x05]. 7 6 5 4 3 2 1 0 d[6] d[5] d[4] d[3] d[2] d[1] d[0]
60 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.38 0x34, 0x35?nr alarm threshold register (snr_alarm_th_low , snr_alarm_th_high) a 2-byte read/write re gister interpreted as a 16-bit, 2 s-complement number . the range of meaningful v alues is limited to positi v e inte gers between 0x0000 and 0x7fff . the v alue of this re gister is compared to the v alue of the snr alarm meter . if the meter reading e xceeds (greater than) this threshold, the lo w_snr interrupt ag is set in the irq source re gister [irq_source; 0x05]. 3.2.39 0x36, 0x37?ursor level register (cursor_level_low , cursor_level_high) a 2-byte read/write re gister interpreted as a 16-bit, 2 s-complement number . the range of meaningful v alues is limited to positi v e inte gers between 0x0000 and 0x2aaa (one-third of the maximum positi v e v alue). the v alue of this re gister represents the e xpected le v el of a noise-free +1 recei v e symbol at the output of the dfe. it is multiplied by 2 to produce the positi v e and ne g ati v e slicing le v els, in addition to zero, used by the symbol detec- tor in four -le v el slicing mode. this v alue is also used to scale the detector output when computing the equalizer error and slicer error signals. the detected symbol (?, ?, +1, +3) is multiplied by the v alue of this re gister to produce the scaled output. 3.2.40 0x38, 0x39?agc t arget register (dagc_target_low , dagc_target_high) a 2-byte read/write re gister interpreted as a 16-bit, 2 s-complement number . the range of meaningful v alues is limited to positi v e inte gers between 0x0000 and 0x7fff . the v alue of this re gister is subtracted from the abso- lute v alue of the recei v e signal at the output of the d a gc function. the dif ference is used as the error input to the d a gc while in the self-adaptation mode. in the d a gc s equalizer -error adaptation mode, the contents of this re gister are not used.
61 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.41 0x3a?ymbol detector modes register (detector_modes) enable_peak_ detector enable peak detector?ead/write control bit that enables the peak detection function when set; disables the function when cleared. when enabled, the peak detector output o v errides the slicer output if the peak detection criteria are met. if the criteria are not met, or if the function is disabled, the slicer output is used and peak detector output is ignored. output_mux_ control[1,0] output multiple x er control?ead/write binary eld that selects the source of the detector output connected to the channel unit recei v e interf ace. scr_out_to_dfe scrambler output to dfe?ead/write control bit that selects the source of the detector output connected to the dfe and timing reco v ery module inputs, and the transmitter s detector loop- back input. when set, this bit selects the scrambler/descrambler function; when cleared, it selects the slicer/peak detector output. two_level t w o-le v el mode?ead/write control bit that selects tw o-le v el mode when set, four -le v el mode when cleared. af fects the slicer and the scrambler/descrambler function. in tw o-le v el mode, the slicer uses a single threshold set at zero to reco v er sign bits only; all magnitude information is lost. scrambler/descrambler updates are slo wed to the symbol rate (half the nor - mal bit rate) to process only sign information as well; all magnitude output bits are sourced with a constant logic zero v alue producing tw o-le v el symbols constrained to +3 and ? v alues. in 4-le v el mode, the slicer uses tw o thresholds deri v ed from the cursor le v el re gister [cursor_le v el_lo w , cursor_le v el_high; 0x36?x37], as well as the zero threshold, to reco v er both sign and magnitude information. the scrambler/descrambler is updated at the full bit rate to process both sign and magnitude bits as well. lfsr_lock lfsr lock?ead/write control bit that enables the auto scrambler synchronization mode (lfsr_lock) in the detector when set; disables this mode when cleared. af fects the beha vior of the scrambler/descrambler function, o v erriding the descr_on setting. when enabled, the scrambler/descrambler is forced into the descrambler mode for 23 c ycles. it is then switched to the scrambled-ones mode for 128 c ycles. while in this mode, the outputs of the scrambler and the slicer/peak detector are compared ag ainst one another . the number of equi v alent bits (equal comparisons) is accumulated and compared to the v alue of the scrambler synchroniza- tion threshold re gister [scr_sync_th; 0x2e]. at an y time during the 128 c ycles, if the count e xceeds the threshold (greater than), the sync interrupt ag is set in the irq source re gister [irq_source; 0x05] and the process terminates with the scrambler/descrambler left in the scrambled-ones mode. (the sync interrupt ag can- 7 6 5 4 3 2 1 0 enable_peak_det ector output_mux_con trol[1] output_mux_con trol[0] scr_out_to_dfe two_level lfsr_lock htur_lfsr descr_on output_mux_control[1,0] detector output to cu receive interface 00 same as scr_out_to_dfe selection. 01 t ransmitter loopback output from cu transmit inter face. 10 scrambler/descrambler output. 11 reser ved.
62 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb not be cleared while lfsr_lock remains high.) after 128 c ycles, if the threshold is not e xceeded, the accumulator is cleared, the scrambler/descrambler re-enters the descrambler mode for another 23 c ycles, and the process repeats until either sync is achie v ed or this mode is dis- abled. once disabled, the sync interrupt ag can be cleared (if acti v e) and the scram- bler/descrambler returns to the mode speci ed by descr_on. htur_lfsr remote unit (htu-r/ntu) polynomial select?ead/write control bit that selects one of tw o feedback polynomials for the scrambler/descrambler . when set, this bit selects the remote unit (htu-r/ntu) recei v e polynomial (x ?3 + x ? + 1); when cleared, is selects the local unit (htu-c/l tu) polynomial (x ?3 + x ?8 + 1). descr_on descrambler/scrambler select?ead/write control bit that con gures the scrambler/descram- bler function as a descrambler when set, and as a scrambler when cleared. as a scrambler , this bit can only generate a scrambled all ones sequence (constant high logic-le v el input); all incoming data is ignored. in the auto scrambler synchronization mode (lfsr_lock = 1), this selection is o v erwritten though the v alue of the control bit is unaf fected. 3.2.42 0x3b?eak detector delay register (peak_detector_delay) a 4-bit read/write re gister interpreted as an unsigned binary number . speci es a number of additional symbol delays inserted in the peak detector input path of the symbol detector . must be set to a v alue that equalizes the total path delay in each of the peak detector and slicer input paths according to the follo wing formula: peak detector delay re gister v alue = d a gc delays + ffe delays ? x ed peak detector input delays. the d a gc and ffe delays are not x ed, b ut result from the microprogrammed implementation of these functions. if used unmodi ed, the y equal 0 and 7, respecti v ely . the x ed peak detector input delay is equal to 3. 3.2.43 0x3c?igital agc modes register (dagc_modes) eq_error_ adaptation equalizer error adaptation?ead/write control bit that selects between the equalizer error adaptation mode when set, and the self-adaptation mode when cleared. equalizer error adapta- tion uses the equalizer error signal produced by the slicer as the d a gc error input signal. in self adaptation, the v alue of the d a gc t ar get re gister [dagc_tar get_lo w , dagc_tar get_high; 0x38?x39] is subtracted from the absolute v alue of the recei v e signal at the output of the d a gc, and this dif ference is used as the error input signal. adapt_coef cient adapt coef cients?ead/write control bit that enables coef cient adaptation when set; dis- ables/freezes adaptation when cleared. coef cient v alues are preserv ed when adaptation is dis- abled. adapt_gain adaptation gain?ead/write control bit that speci es the adaptation g ain. when set, the adaptation g ain is eight times higher than when cleared. 7 6 5 4 3 2 1 0 d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 eq_error_ adaptation adapt_coef cient adapt_gain
63 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.44 0x3d?eed for ward equalizer modes register (ffe_modes) adapt_last_coeff adapt last coef cient?ead/write control bit enables adaptation of the last (oldest) coef - cient only when set; allo ws all coef cient adaptation when cleared. ov erall coef cient adapta- tion must be enabled (adapt_coef cients = 1) for this beha vior to occur . if coef cient adaptation is disabled (adapt_coef cients = 0), the v alue of this control bit is not used. zero_coef cients zero coef cients?ead/write control bit which, with coef cient adaptation enabled (adapt_coef cients = 1), continuously zeros all coef cients when set; allo ws normal coef - cient updates when cleared. if coef cient adaptation is disabled (adapt_coef cients = 0), this control bit has no af fect. this beha vior dif fers slightly from the similar function (zero_coef cients) of the lec, nec, and dfe lters. adapt_coef cents adapt coef cients?ead/write control bit enables coef cient adaptation when set; dis- ables/freezes adaptation when cleared. coef cient v alues are preserv ed when adaptation is dis- abled. this o v erall coef cient adaptation must be enabled for adapt_last_coef f to ha v e an af fect. adapt_gain adaptation gain?ead/write control bit speci es the adaptation g ain. when set, the adapta- tion g ain is four times higher than when cleared. 3.2.45 0x3e?rror predictor modes register (ep_modes) zero_output zero output?ead/write control bit which, when set, zeros the error predictor correction sig- nal before subtraction from the input signal. achie v es the af fect of disabling, or bypassing, the error predictor function. does not disable coef cient adaptation. when cleared, normal error predictor operation is performed. zero_coef cients zero coef cients?ead/write control bit which, with coef cient adaptation enabled (adapt_coef cients = 1), continuously zeros all coef cients when set; allo ws normal coef - cient updates when cleared. if coef cient adaptation is disabled (adapt_coef cients = 0), this control bit has no af fect. this beha vior dif fers slightly from the similar function (zero_coef cients) of the lec, nec, and dfe lters. adapt_coef cents adapt coef cients?ead/write control bit enables coef cient adaptation when set; dis- ables/freezes adaptation when cleared. coef cient v alues are preserv ed when adaptation is dis- abled. adapt_gain adaptation gain?ead/write control bit speci es the adaptation g ain. when set, the adapta- tion g ain is four times higher than when cleared. 7 6 5 4 3 2 1 0 adapt_last_coeff zero_coef cents adapt_ coef cents adapt_gain 7 6 5 4 3 2 1 0 zero_output zero_coef cients adapt_ coef cients adapt_gain
64 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.46 0x40, 0x41?hase detector meter register (pdm_low , pdm_high) a 2-byte read-only re gister containing the 16 msbs of the 26-bit, 2 s-complement phase detector meter accu- mulator . this meter sums the output of the timing reco v ery module s phase detector?rior to being of fset by the phase of fset re gister [pll_phase_of fset_lo w , pll_phase_of fset_high; 0x24, 0x25]? v er each meter t imer countdo wn interv al. automatically loaded at the end of each interv al, the meter re gister must be read lo w byte rst, follo wed by high byte, unseparated by an y other meter -re gister read access. 3.2.47 0x42?ver ow meter register (over ow_meter) a single-byte read-only re gister containing all 8 bits of the unsigned o v er o w meter accumulator . this meter counts the number of adc o v er o w conditions which occur during each meter t imer countdo wn interv al, lim- ited to a maximum count of 255 (0xff). the meter re gister is automatically loaded at the end of each count- do wn interv al. 3.2.48 0x44, 0x45?c level meter register (dc_meter_low , dc_meter_high) a 2-byte read-only re gister containing the 16 msbs of the 32-bit, 2 s-complement dc-le v el meter accumulator . this meter sums the v alue of the recei v e signal input path?fter format con v ersion and dc of fset correction b ut before echo cancellation? v er each meter t imer countdo wn interv al. automatically loaded at the end of each interv al, the meter re gister must be read lo w byte rst, follo wed by high byte, unseparated by an y other meter -re gister read access. 7 6 5 4 3 2 1 0 d[17] d[16] d[15] d[14] d[13] d[12] d[11] d[10] d[25] d[24] d[23] d[22] d[21] d[20] d[19] d[18] 7 6 5 4 3 2 1 0 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24]
65 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.49 0x46, 0x47?ignal level meter register (slm_low , slm_high) a 2-byte read-only re gister containing 16 msbs of the 32-bit unsigned signal-le v el meter accumulator . this meter sums the absolute v alue of the recei v e signal input path?fter format con v ersion and dc of fset correc- tion b ut before echo cancellation (same point as the dc le v el meter)? v er each meter t imer countdo wn inter - v al. automatically loaded at the end of each interv al, the meter re gister must be read lo w byte rst, follo wed by high byte, unseparated by an y other meter -re gister read access. 3.2.50 0x48, 0x49?ar -end level meter register (felm_low , felm_high) a 2-byte read-only re gister containing 16 msbs of the 32-bit unsigned f ar -end le v el meter accumulator . this meter sums the absolute v alue of the recei v e signal path?fter echo cancellation b ut before the d a gc func- tion? v er each meter t imer countdo wn interv al. automatically loaded at the end of each interv al, the meter re gister must be read lo w byte rst, follo wed by high byte, unseparated by an y other meter -re gister read access. 3.2.51 0x4a, 0x4b?oise level histogram meter register (noise_histogram_low , noise_histogram_high) a 2-byte read-only re gister containing all 16 bits of the unsigned noise-le v el histogram meter accumulator . this meter counts the number of high-noise-le v el conditions which occur during each meter t imer countdo wn inter - v al. a high-noise-le v el condition is de ned as the absolute v alue of the slicer error signal e xceeding (greater than) the threshold speci ed in the noise-le v el histogram threshold re gister [0x2a, 2b]. automatically loaded at the end of each countdo wn interv al, the meter re gister must be read lo w byte rst, follo wed by high byte, unseparated by an y other meter -re gister read access. 7 6 5 4 3 2 1 0 d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 7 6 5 4 3 2 1 0 d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] 7 6 5 4 3 2 1 0 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8]
66 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.52 0x4c, 0x4d?it error rate meter register (ber_meter_low , ber_meter_high) a 2-byte read-only re gister containing all 16 bits of the unsigned bit-error -rate meter accumulator . this meter counts the number of error -free bits reco v ered by the detector during each meter t imer countdo wn interv al. an error -free bit is de ned as a match (equal comparison) of the detector s slicer/peak detector output and its scrambler/descrambler output, when operating as a scrambler . when operating as a descrambler , the meter sim- ply counts the number of logic ones produced by the descrambler . the meter re gister is automatically loaded at the end of each countdo wn interv al, and must be read lo w byte rst, follo wed by high byte, unseparated by an y other meter -re gister read access. 3.2.53 0x4e?ymbol histogram meter register (symbol_histogram) a single-byte read-only re gister containing 8 msbs of the 16-bit unsigned symbol histogram meter accumula- tor . this meter counts the number of plus-one or minus-one symbols (+1, ?) detected during each meter t imer countdo wn interv al. no increment occurs when a plus-three or minus-three symbol (+3, ?) is detected. the meter re gister is automatically loaded at the end of each countdo wn interv al. 3.2.54 0x50, 0x51?oise level meter register (nlm_low , nlm_high) a 2-byte read-only re gister containing 16 msbs of the 32-bit unsigned noise-le v el meter accumulator . this meter sums the absolute v alue of the detector s slicer -error signal o v er each meter t imer countdo wn interv al. automatically loaded at the end of each interv al, the meter re gister must be read the lo w byte rst, follo wed by high byte, unseparated by an y other meter -re gister read access. 7 6 5 4 3 2 1 0 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] 7 6 5 4 3 2 1 0 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24]
67 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.55 0x5e, 0x5f?pll frequency register (pll_frequency_low , pll_frequency_high) a 2-byte read/write re gister comprising the 16 msbs of the 31-bit, 2 s-complement timing reco v ery loop com- pensation lter accumulator . t reated much lik e a meter re gister , the frequenc y re gister must be read lo w byte rst, follo wed by high byte, unseparated by an y timing-function or meter -re gister read access. writes must occur in the same order , with the lo w byte written rst, follo wed by the high byte. write accesses may be sepa- rated by an y number of other read or write accesses. 3.2.56 0x70?ec read t ap select register (linear_ec_tap_select_read) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 59 decimals. when written, it causes the selected 32-bit coef cient of the lec to be subsequently loaded into the access data re gister [access_data_byte[3:0]; 0x7c?x7f] within tw o symbol periods. does not af fect the v alue of the coef cient. 3.2.57 0x71?ec write t ap select register (linear_ec_tap_select_write) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 59 decimals. when written, it causes all 32 bits of the access data re gister [access_data_byte[3:0]; 0x7c?x7f] to be sub- sequently written to the selected lec coef cient within tw o symbol periods. does not af fect the v alue of the access data re gister . 3.2.58 0x72?ec read t ap select register (nonlinear_ec_tap_select_read) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 63 decimals. when written, it causes the selected 14-bit coef cient of the nec to be subsequently loaded into the lo west- order bits of the access data re gister [access_data_byte[3:0]; 0x7c?x7f] within tw o symbol periods. does not af fect the v alue of the coef cient. 7 6 5 4 3 2 1 0 d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[15] d[30] d[29] d[28] d[27] d[26] d[25] d[24] d[23] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0]
68 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.59 0x73?ec write t ap select register (nonlinear_ec_tap_select_write) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 63 decimals. when written, it causes the lo west-order 14 bits of the access data re gister [access_data_byte[3:0]; 0x7c 0x7f] to be subsequently written to the selected nec coef cient within tw o symbol periods. does not af fect the v alue of the access data re gister . 3.2.60 0x74?fe read t ap select register (dfe_tap_select_read) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 57 decimals. when written, it causes the selected 16-bit coef cient of the dfe to be subsequently loaded into the lo west- order bits of the access data re gister [access_data_byte[3:0]; 0x7c?x7f] within tw o symbol periods. does not af fect the v alue of the coef cient. 3.2.61 0x75?fe write t ap select register (dfe_tap_select_write) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 57 decimals. when written, it causes the lo west-order 16 bits of the access data re gister [access_data_byte[3:0]; 0x7c 0x7f] to be subsequently written to the selected dfe coef cient within tw o symbol periods. does not af fect the v alue of the access data re gister . 3.2.62 0x76?cratch pad read t ap select (sp_tap_select_read) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 63 decimals. when written, it causes the selected 8-bit scratch pad memory location to be subsequently loaded into the lo w- est-order bits of the access data re gister [access_data_byte[3:0]; 0x7c?x7f] within tw o symbol periods. does not af fect the v alue of the memory . 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0]
69 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.63 0x77?cratch pad write t ap select (sp_tap_select_write) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 63 decimals. when written, it causes the lo west-order 8 bits of the access data re gister [access_data_byte[3:0]; 0x7c 0x7f] to be subsequently written to the selected scratch pad memory location within tw o symbol periods. does not af fect the v alue of the access data re gister . 3.2.64 0x78?qualizer read select register (eq_add_read) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 47 decimals. when written, it causes the selected 16-bit location of the equalizer re gister le to be subsequently loaded into the lo west-order bits of the access data re gister [access_data_byte[3:0]; 0x7c?x7f] within tw o symbol peri- ods. does not af fect the v alue of the re gister le location. an address map of the shared re gister le, as de ned by the f actory-deli v ered microcode, is sho wn belo w . 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] d[5:0] stored parameter decimal binary 0? 00 0000?0 0111 ffe coef cients 0? 8?5 00 1000?0 1111 ffe data t aps 0? 16?0 01 0000?1 0100 ep coef cients 0? 21?5 01 0101?1 1001 ep data t aps 0? 26 01 1010 dagc gain - least-signi cant w ord 27 01 1011 dagc gain - most-signi cant w ord 28 01 1100 dagc output 29 01 1101 ffe output 30 01 1110 dagc input 31 01 1111 ffe output, delayed 1 symbol period 32 10 0000 dagc error signal 33 10 0001 equalizer error signal 34 10 0010 slicer error signal 35?7 10 0011?0 1111 reser ved
70 3.0 registers 3.1 conventions bt8960 single-chip 2b1q t ransceiver n8960dsb 3.2.65 0x79?qualizer write select register (eq_add_write) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 47 decimals. when written, it causes the lo west-order 16 bits of the access data re gister [access_data_byte[3:0]; 0x7c 0x7f] to be subsequently written to the selected equalizer re gister le location within tw o symbol periods. does not af fect the v alue of the access data re gister . an address map of the shared re gister le, as de ned by the f ac- tory-deli v ered microcode, is sho wn belo w . 3.2.66 0x7a?qualizer microcode read select register (eq_microcode_add_read) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 63 decimals. when written, it causes the selected 32-bit location of the equalizer microprogram store to be subsequently loaded into the access data re gister [access_data_byte[3:0]; 0x7c?x7f] within tw o symbol periods. does not af fect the v alue of the microprogram store location. 3.2.67 0x7b?qualizer microcode write select register (eq_microcode_add_write) a 6-bit read/write re gister representing an unsigned binary address de ned o v er a range of 0 to 63 decimals. when written, it causes all 32 bits of the access data re gister [access_data_byte[3:0]; 0x7c?x7f] to be sub- sequently written to the selected equalizer microprogram store location within tw o symbol periods. does not af fect the v alue of the access data re gister . f actory-de v eloped equalizer microcode is included with the no-fee licensed hdsl transcei v er softw are a v ailable from rockwell. 3.2.68 0x7c?x7f?ccess data register (access_data_byte3:0) a 4-byte read/write re gister stores lter coef cient, equalizer re gister le, and equalizer microprogram store contents during indirect accesses to these ram-based locations. writes to addresses 0x70 through 0x7b, utilize the contents of this shared re gister as speci ed in each of the indi vidual re gister descriptions. 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0] 7 6 5 4 3 2 1 0 d[5] d[4] d[3] d[2] d[1] d[0]
71 n8960dsb 4.0 electrical & mechanical specifications 4.1 absolute maximum ratings stresses abo v e those listed may cause permanent damage to the de vice. this is a stress rating only . functional operation of the de vice at these or an y other conditions be yond those listed in the operational sections of this speci cation is not implied. exposure to absolute maximum rating conditions for e xtended periods may af fect de vice reliability . t able 4-1. absolute maximum ratings symbol parameter minimum maximum units v supply supply v oltage (1) ?.5 +7 v v i input v oltage on any signal pin (2) ?.5 v dd2 + 0.5 v t st storage t emperature ?5 +125 ?c t vsol v apor -phase soldering t emperature (1 minute) +220 ?c notes: (1). v dd1 , v dd2 , relative to dgnd. v aa relative to agnd. (2). relative to dgnd.
72 4.0 electrical & mechanical speci cations 4.2 recommended operating conditions bt8960 single-chip 2b1q t ransceiver n8960dsb 4.2 recommended operating conditions t able 4-2. recommended operating conditions symbol parameter minimum typical maximum units v dd1 digital core-logic supply v oltage 4.75 5.0 5.25 v v dd2 digital i/o-buffer supply v oltage 4.75 5.0 5.25 v v aa analog supply v oltage 4.75 5.0 5.25 v v ih high-level input v oltage 2.0 v dd2 + 0.3 v v il low-level input v oltage ?.3 +0.8 v v ihx high-level input v oltage for xt ali / mclk 0.8*v dd2 v dd2 + 0.3 v v ilx low-level input v oltage for xt ali / mclk ?.3 0.2*v dd2 v c l output capacitive loading (1) 60 pf t a ambient operating t emperature (2) ?0 +85 ?c notes: (1). capacitive loading over which all digital output switching characteristics are guaranteed. (2). still-air temperature range over which all electrical characteristics and timing requirements/characteristics are guaran- teed.
73 4.0 electrical & mechanical speci cations 4.3 electrical characteristics bt8960 single-chip 2b1q t ransceiver n8960dsb 4.3 electrical characteristics t ypical characteristics measured at nominal operating conditions: t a = 25 ?c; v dd/aa = 5.0 v minimum/maxi- mum characteristics guaranteed o v er e xtreme operating conditions: min t a max; min v dd/aa max. t able 4-3. electrical characteristics symbol parameter minimum typical maximum units v oh high-level output v oltage @ i oh = ?00 m a 2.4 v v oll low-level output v oltage @ i ol = 6 ma ( irq and ready ) 0.4 v v ol low-level output v oltage @ i ol = 3 ma (all other outputs) 0.4 v i i input leakage current @ v ss2 v i v dd2 10 m a i oz high-impedance output leakage current @ v ss2 v o v dd2 10 m a i pr resistive pull-up current @ v i = v ss2 (tdi and tms) ?00 ?00 m a i tot al t otal supply current @ f qclk = 208 khz (n=6) (1) 133 147 ma i tot al t otal supply current @ f qclk = 144 khz (n=4) (1) 120 131 ma i tot al t otal supply current @ f qclk = 80 khz (n=2) (1) 106 117 ma i pd t otal power -down current @ f qclk = 208 khz (n=6) (2) tbd ma i pd t otal power -down current @ f qclk = 144 khz (n=4) (2) tbd ma i pd t otal power -down current @ f qclk = 80 khz (n=2) (2) tbd ma c i input capacitance 10 pf c oz high-impedance output capacitance 10 pf notes: (1). i total = i dd1 + i dd2 + i aa during normal operation. (2). i tot al = i dd1 + i dd2 + i aa during power -down operation.
74 4.0 electrical & mechanical speci cations 4.4 clock t iming bt8960 single-chip 2b1q t ransceiver n8960dsb 4.4 clock t iming t able 4-4. external clock t iming requirements (mclk) symbol parameter minimum maximum units 1 mclk period (t mclk ) (1) 75 196 ns 2 mclk pulse-width low 30 ns 3 mclk pulse-width high 30 ns note: (1). if an external clock is applied to xtali/mclk, it is referred to as mclk. figure 4-1. mclk t iming requirements 3 2 1 mclk t able 4-5. hclk switching characteristics symbol parameter minimum typical maximum units 4 hclk period (t hclk ), hclk_freq[1:0] = ?0? or ?1?(n=6) (1) t qclk ? 64 t qclk ? 64 t qclk ? 64 5 hclk period (t hclk ), hclk_freq[1:0] = ?1? (n=2) (1) t qclk ? 16 t qclk ? 16 t qclk ? 16 6 hclk period (t hclk ), hclk_freq[1:0] = ?0? (n=4) (1) t qclk ? 32 t qclk ? 32 t qclk ? 32 7 hclk pulse-width high t hclk ? 2 ?10 t hclk ? 2 t hclk ? 2 + 10 ns 8 hclk pulse-width low t hclk ? 2 ?10 t hclk ? 2 t hclk ? 2 + 10 ns notes: (1). the hclk_freq[1:0] control bits are located in the serial monitor source select register [addr. 0x01].
75 4.0 electrical & mechanical speci cations 4.4 clock t iming bt8960 single-chip 2b1q t ransceiver n8960dsb t able 4-6. symbol clock (qclk) switching characteristics symbol parameter minimum maximum units 9 qclk period (t qclk ) (1) k x t hclk k x t hclk 10 qclk pulse-width high t qclk ? 2 ? 20 t qclk ? 2 + 20 ns 11 qclk pulse-width low t qclk ? 2 ? 20 t qclk ? 2 + 20 ns 12 qclk hold after hclk rising edge ?0 13 qclk delay after hclk high 20 note: (1). k = 16, 32 or 64 according to hclk_freq[1,0]. qclk can be frequency locked to the incoming data symbol rate. figure 4-2. clock control t iming 4,5,6 11 10 9 7 8 12 13 hclk qclk
76 4.0 electrical & mechanical speci cations 4.5 channel unit interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb 4.5 channel unit interface t iming t able 4-7. channel unit interface t iming requirements, parallel master mode symbol parameter minimum maximum units 14 tq[1,0] setup prior to qclk falling edge 100 ns 15 tq[1,0] hold after qclk low 25 ns t able 4-8. channel unit interface switching characteristics, parallel master mode symbol parameter minimum maximum units 16 rq[1,0] hold after qclk rising edge ?0 ns 17 rq[1,0] delay after qclk high 50 ns figure 4-3. channel unit interface t iming, parallel master mode 14 15 16 17 rq[1,0] qclk tq[1,0]
77 4.0 electrical & mechanical speci cations 4.5 channel unit interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb t able 4-9. channel unit interface t iming requirements, parallel slave mode symbol parameter minimum maximum units 18 tbclk, rbclk period (1) t qclk t qclk 19 tbclk , rbclk pulse-width high t qclk ? 4 20 tbclk , rbclk pulse-width low t qclk ? 4 21 tq[1,0] setup prior to tbclk active edge (2) 25 ns 22 tq[1,0] hold after tbclk high/low (2) 25 ns notes: (1). tbclk and rbclk must be frequency locked to qclk though they may have independent phase relationships to qclk and to one another. (2). tbclk polarity (edge sensitivity) is programmable through the cu inter face modes register [cu_inter face_modes 0x06]. t able 4-10. channel unit interface switching characteristics, parallel slave mode symbol parameter minimum maximum units 23 rq[1,0] hold after rbclk active edge (1) 0 ns 24 rq[1,0] delay after rbclk high/low (1) 100 ns notes: (1). rbclk polarity (edge sensitivity) is programmable through the cu interface modes register [cu_interface_modes; 0x06]. figure 4-4. channel unit interface t iming, parallel slave mode note: tbclk and rbclk polarities are programmable through the cu interface modes register. the figure depicts both clocks programmed to falling-edge active. rq[1:0] tbclk tq[1:0] rbclk 18 19 20 21 22 23 24 18 19 20
78 4.0 electrical & mechanical speci cations 4.5 channel unit interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb t able 4-11. channel unit interface t iming requirements, serial mode symbol parameter minimum maximum units 25 tda t setup prior to bclk falling edge 100 ns 26 tda t hold after bclk low 25 ns t able 4-12. channel unit interface switching characteristics, serial mode symbol parameter minimum maximum units 27 bclk period t qclk ? 2 t qclk ? 2 28 bclk pulse-width high t qclk ? 4 ?20 t qclk ? 4 + 20 ns 29 bclk pulse-width low t qclk ? 4 ?20 t qclk ? 4 + 20 ns 30 bclk hold after hclk rising edge 0 ns 31 bclk delay after hclk high 50 ns 32 rda t , qclk hold after bclk rising edge ?0 ns 33 rda t , qclk delay after bclk high 50 ns figure 4-5. channel unit interface t iming, serial mode hclk bclk td a t qclk rd a t 25 26 27 28 29 30 31 32 33
79 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb 4.6 microcomputer interface t iming t able 4-13. microcomputer interface t iming requirements symbol parameter minimum maximum units 34 ale pulse-width high 30 ns 35 address setup prior to ale falling edge (1) 12 ns 36 address hold after ale low (1) 5 ns 37 ale low prior to write strobe falling edge (2) 20 ns 38 ale low prior to read strobe falling edge (3,4) ?7 ns 39 write strobe pulse-width low (2,5) 2*tmclk +25 ns 40 read strobe pulse-width low (3,5) 2*tmclk +25 ns 41 data in setup prior to write strobe rising edge (2) 30 ns 42 data in hold after write strobe high (2) 5 ns 43 r/ w setup prior to read/write strobe falling edge 10 ns 44 r/ w hold after read/write strobe high 10 ns 45 ale falling edge after write strobe high 20 ns 46 ale falling edge after read strobe high 20 ns 47 rst pulse-width low 50 ns 48 write strobe rising edge after ready low 0 ns notes: (1). address is defined as ad[7:0] when muxed = 1, and addr[7:0] when muxed = 0. (2). in intel mode, write strobe is de ned as wr and cs asserted . in motorola mode, it is de ned as ds and cs asserted when r/ w is low . (3). in intel mode, read strobe is de ned as rd and cs asserted . in motorola mode, it is de ned as ds and cs asserted when r/ w is high. (4). parameter 38 is ?7 ns only if separate address and data busses are used (i.e., muxed = 0). if muxed = 1, then parameter 38 is 20 ns. (5). the timing listed is for the synchronous mode of the mci. it can also be set to synchronous mode by setting bit 0 of the reser ved2 register (address 0x0f) to a 1. in this case the minimum timing changes to 40 us for symbol 39, and 50 us for symbols 40 and 50. synchronous mode is preferred because it reduces internal switching noise, however no signif- icant per formance degradation has been measured as a result of using the asynchronous mode.
80 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb t able 4-14. microcomputer interface switching characteristics symbol parameter minimum maximum units 49 data out enable (low z) after read strobe falling edge (1) 2 ns 50 data out v alid after read strobe low (1,7) 2* tmclk +25 ns 51 data out hold after read strobe rising edge (1) 2 ns 52 data out disable (high z) after read strobe high (1) 25 ns 53 irq hold after write strobe rising edge (2,3) 5 ns 54 irq delay after write strobe high (2,3) tqclk ? 32 + 20 ns 55 internal register delay after write strobe high (3,4) tqclk ? 32 ns 56 internal ram delay after write strobe high (3,5) 2*tqclk ns 57 access data register delay after write strobe high (3,6) 2* tqclk ns 58 ready falling edge after write strobe low (3) 0 2*tmclk +25 ns 59 ready rising edge after write strobe high (3) 0 50 ns 60 ready falling edge after read strobe low (1) 0 2*tmclk +25 ns 61 ready rising edge after read strobe high (1) 0 50 ns 62 data out v alid after ready low 10 ns notes: (1). read strobe is defined as rd and cs asserted in intel mode, and ds and cs asserted when r/ w is high in motorola mode. (2). when writing an interrupt mask or status register . (3). write strobe is de ned as wr and cs asserted in intel mode, and ds and cs asserted when r/ w is low in motorola mode. (4). writes to internal registers are synchronized to an internal 64-times symbol-rate clock. data is available for reading after the speci ed time. this parameter may extend the overall read access time from internal register locations under high bus speed/low symbol rate conditions. (5). when per forming an indirect write to ram-based locations using a write select register [odd addresses: 0x71?x7b] and the access data register . subsequent writes to any read/write select register or the access data register , as initiated by a write strobe falling edge, is prohibited for the speci ed time. this parameter will extend the overall write access time to ram-based locations under normal bus speed/symbol rate conditions. (6). when per forming an indirect read from ram-based locations using a read select register [even addresses: 0x70?x7a] and the access data register . subsequent writes to any read/write select register , as initiated by a write strobe falling edge, is prohibited for the speci ed time. data is available for reading from the access data register after the speci ed time. this parameter will extend the overall read access time from ram-based locations under normal bus speed/sym- bol rate conditions. direct writes to the access data register are as speci ed for internal registers. (7). the timing listed is for the synchronous mode of the mci. it can also be set to synchronous mode by setting bit 0 of the reser ved2 register (address 0x0f) to a 1. in this case the minimum timing changes to 40 us for symbol 39, and 50 us for symbols 40 and 50. synchronous mode is preferred because it reduces internal switching noise, however no signif- icant per formance degradation has been measured as a result of using the asynchronous mode.
81 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb figure 4-6. mci write t iming, intel mode (motel = 0) wr ite strobe ale 35 36 37 34 39 41 42 address data (input) 45 ad[7:0] or addr[7:0] ready 58 59 48 figure 4-7. mci write t iming, motorola mode (motel = 1) ad[7:0] wr ite strobe ale 35 36 37 34 39 41 42 r/ w 43 44 address data (input) 45 58 59 or addr[7:0] ready 48
82 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb figure 4-8. mci read t iming, intel mode (motel = 0) read strobe ale 35 36 34 40 51 address data (output) 49 50 52 46 ad[7:0] or addr[7:0] 38 ready 61 60 62 figure 4-9. mci read t iming, motorola mode (motel = 1) read strobe ale 35 36 34 40 51 address data (output) 49 50 52 r/ w 43 44 46 ad[7:0] or addr[7:0] 38 ready 61 60 62
83 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb figure 4-10. internal write t iming irq wr ite 53 54 strobe 55 56 inter nal register inter nal ram access data register 57
84 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb 4.6.1 t est and diagnostic interface t iming t able 4-15. t est and diagnostic interface t iming requirements symbol parameter minimum maximum units 56 tck pulse-width high 80 ns 57 tck pulse-width low 80 ns 58 tms, tdi setup prior to tck rising edge (1) 20 ns 59 tms, tdi hold after tck high (1) 20 ns note: (1). also applies to functional inputs for sample/preload and extest instructions. t able 4-16. t est and diagnostic interface switching characteristics symbol parameter minimum maximum units 60 tdo hold after tck falling edge (1) 0 ns 61 tdo delay after tck low (1) 50 ns 62 tdo enable (low z) after tck falling edge (1) 2 ns 63 tdo disable (high z) after tck low (1) 25 ns 64 smon hold after hclk rising edge (2) 0 ns 65 smon delay after hclk high (2) 50 ns notes: (1). also applies to functional outputs for the extest instruction. (2). hclk must be programmed to operate at 16 times the symbol rate (16 x f qclk ).
85 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb figure 4-11. jt ag interface t iming 56 57 58 59 60 61 62 63 tdo tck tdi tms figure 4-12. smon t iming 64 65 hclk smon
86 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb 4.6.2 analog speci cations t able 4-17. receiver analog requirements and speci cations parameter comments min typ max units input signals rxp , rxn, rxbp , and rxbn input v oltage range balanced differential ?.5 +4.5 v input resistance dc to 1 mhz 28 k w common mode v oltage vcomi 0.4*v aa v ariable gain ampli er (vga) six gains from 0 db to +15 db gain step 2.55 3.0 3.42 db gain error 10 % analog-to-digital converter output symbol rate (f qclk ) qclk frequency (data rate/2) 75 210 khz differential v oltage range (full scale input, fs) (1) (v rxp ? rxn )?v rxbp ? rxbn ) 5.4 6.0 6.6 v p t iming recover y pll pull-in range 64 ppm note: (1). corresponds to the voltages that will produce a full scale reading from the adc when the vga gain equals o db. input voltage range is reduced proportionally as vga gain is increased .
87 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb t able 4-18. t ransmitter analog requirements and speci cations parameter comments min typ max units t ransmit symbol rate (f qclk ) qclk frequency (data rate/2) 75 210 khz pulse t emplate (1, 2,3) see figure 4-13 , r l = 135 w a verage power (1, 2,4) dc to 2xf qclk , r l = 135 w , 0db gain setting 13.4 14.0 dbm gain adjustment step controlled by t ransmit gain register [0x29]. seven steps above and eight steps below 0 db. 0.17 0.20 0.24 db output referred offset v oltage 25 mv output current 125 ma common-mode v oltage vcomo v aa/2 v output impedance (1) dc to 1 mhz 2 w linearity at output symbol peak 0.01 %fsr (5) harmonic distortion 3 khz, 3.4 v peak sine w ave output, r l = 0 w ?0 db notes: (1). guaranteed by design and characterization . (2). see 4-14 of the t est conditions section of this datasheet for test cir cuit. (3). measured after the transmitter is calibrated by writing the value in the t ransmitter calibration register [tx_calibrate; 0x28] to the t ransmitter gain register [tx_gain; 0x29]. (4). measured with a pseudo-random code sequence of pulses. (5). fsr is full scale range.
88 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb figure 4-13. t ransmitted pulse t emplate b = 1.07 c = 1.00 d = 0.93 ?.4t 0.4t 1.25t e = 0.03 g = ?.16 0.5t ?.6t ?.2t a = 0.01 f = ?.01 14t a = 0.01 f = ?.01 h = ?.05 50t t = 1/f qclk t able 4-19. t ransmitted pulse t emplate normalized level quaternary symbols +3 +1 ? ? a 0.01 0.0264 0.0088 ?.0088 ?.0264 b 1.07 2.8248 0.9416 ?.9416 ?.8248 c 1.00 2.6400 0.8800 ?.8800 ?.6400 d 0.93 2.4552 0.8184 ?.8184 ?.4552 e 0.03 0.0792 0.0264 ?.0264 ?.0792 f ?.01 ?.0264 ?.0088 0.0088 0.0264 g ?.16 ?.4224 ?.1408 0.1408 0.4224 h ?.05 ?.1320 ?.0440 0.0440 0.1320
89 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb 4.6.3 t est conditions figure 4-14. t ransmitter t est circuit note: see table 4-20 for c8 and transformer values. txp (71) txn (74) + + - - txldip (69) txldin (70) 3.01 k w 1 k w 1 k w 3.01 k w 1 k w 1 k w txpsp (67) txpsn (68) c8 line dr iv er line transformer + - r l 1:2 + _ 16.2 w 16.2 w
90 4.0 electrical & mechanical speci cations 4.6 microcomputer interface t iming bt8960 single-chip 2b1q t ransceiver n8960dsb t able 4-20. t ransmitter t est circuit component v alues component data rate 288 kbps 416 kbps c8 1.8 nf 4.7 nf l (primar y inductance - line side) 5.0 mh 3.5 mh figure 4-15. standard output load (t otem pole and three-state outputs) cl f rom bt8960 iol ioh 1.5 v figure 4-16. open-drain output load ( irq ) f rom bt8960 c l i od v dd2
91 4.0 electrical & mechanical speci cations 4.7 t iming measurements bt8960 single-chip 2b1q t ransceiver n8960dsb 4.7 t iming measurements the input w a v eforms are sho wn in figure 4-17 . output w a v eforms are displayed in figures 4-18 and 4-19 . figure 4-17. input w aveforms for t iming t ests 3 v 0 v 2.0 v 0.8 v input high input lo w input high input lo w figure 4-18. output w aveforms for t iming t ests ? vdd ? 0 v 2.4 v 0.4 v output high output lo w output high output lo w
92 4.0 electrical & mechanical speci cations 4.8 mechanical speci cations bt8960 single-chip 2b1q t ransceiver n8960dsb 4.8 mechanical speci cations figure 4-19. output w aveforms for three-state enable and disable t ests 1.7 v 1.3 v output disab led output enab led 1.5 v v oh - 0.2 v v ol + 0.2 v output disab led
93 4.0 electrical & mechanical speci cations 4.8 mechanical speci cations bt8960 single-chip 2b1q t ransceiver n8960dsb figure 4-20. 100-pin plastic quad flat pack
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